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    <title>topic Re: S32G274 Debugging CAN Communication After Dual-Core Boot-up in S32G</title>
    <link>https://community.nxp.com/t5/S32G/Re-S32G274-Debugging-CAN-Communication-After-Dual-Core-Boot-up/m-p/2315057#M16028</link>
    <description>&lt;P&gt;1. The phenomenon I observed is that after A core loads PFE and starts up, the flexcan0 of M7 cannot communicate normally. The specific situation is that at this time, when I use the cantest upper computer to send CAN messages to flexcan0, the message can be sent successfully, but the flexcan0 of M7 does not respond at all and does not send anything externally. Therefore, I infer that M7 has crashed at this time. So the two registers you mentioned are definitely normal.&lt;BR /&gt;2. I would like to ask how to read the values of relevant registers after starting Linux. What command is it?&lt;BR /&gt;3. After enabling the PFE firmware loading, which files and functions in the program are the specific loading processes? If I need to change HIL1 to HIL0 in it, how should I do it?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;(Note: This thread is branched from&amp;nbsp;&lt;A href="https://community.nxp.com/t5/S32G/S32G274-Debugging-CAN-Communication-After-Dual-Core-Boot-up/m-p/2306579/highlight/true#M15942" target="_blank"&gt;https://community.nxp.com/t5/S32G/S32G274-Debugging-CAN-Communication-After-Dual-Core-Boot-up/m-p/2306579/highlight/true#M15942&lt;/A&gt;&amp;nbsp;)&lt;/P&gt;</description>
    <pubDate>Mon, 16 Feb 2026 14:27:39 GMT</pubDate>
    <dc:creator>sdx111</dc:creator>
    <dc:date>2026-02-16T14:27:39Z</dc:date>
    <item>
      <title>Re: S32G274 Debugging CAN Communication After Dual-Core Boot-up</title>
      <link>https://community.nxp.com/t5/S32G/Re-S32G274-Debugging-CAN-Communication-After-Dual-Core-Boot-up/m-p/2315057#M16028</link>
      <description>&lt;P&gt;1. The phenomenon I observed is that after A core loads PFE and starts up, the flexcan0 of M7 cannot communicate normally. The specific situation is that at this time, when I use the cantest upper computer to send CAN messages to flexcan0, the message can be sent successfully, but the flexcan0 of M7 does not respond at all and does not send anything externally. Therefore, I infer that M7 has crashed at this time. So the two registers you mentioned are definitely normal.&lt;BR /&gt;2. I would like to ask how to read the values of relevant registers after starting Linux. What command is it?&lt;BR /&gt;3. After enabling the PFE firmware loading, which files and functions in the program are the specific loading processes? If I need to change HIL1 to HIL0 in it, how should I do it?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;(Note: This thread is branched from&amp;nbsp;&lt;A href="https://community.nxp.com/t5/S32G/S32G274-Debugging-CAN-Communication-After-Dual-Core-Boot-up/m-p/2306579/highlight/true#M15942" target="_blank"&gt;https://community.nxp.com/t5/S32G/S32G274-Debugging-CAN-Communication-After-Dual-Core-Boot-up/m-p/2306579/highlight/true#M15942&lt;/A&gt;&amp;nbsp;)&lt;/P&gt;</description>
      <pubDate>Mon, 16 Feb 2026 14:27:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Re-S32G274-Debugging-CAN-Communication-After-Dual-Core-Boot-up/m-p/2315057#M16028</guid>
      <dc:creator>sdx111</dc:creator>
      <dc:date>2026-02-16T14:27:39Z</dc:date>
    </item>
    <item>
      <title>Re: S32G274 Debugging CAN Communication After Dual-Core Boot-up</title>
      <link>https://community.nxp.com/t5/S32G/Re-S32G274-Debugging-CAN-Communication-After-Dual-Core-Boot-up/m-p/2318649#M16029</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAEQAA" data-processed="true"&gt;
&lt;DIV style="display: contents;" data-subtree="aimfl,mfl" data-processed="true"&gt;The M7 core appears to crash due to a conflict with the PFE (Packet Forwarding Engine) subsystem after Linux boots on the A53 core, as PFE and Ethernet/CAN resources can be mutually exclusive on the S32G platform&lt;/DIV&gt;
.&lt;SPAN class="uJ19be notranslate" data-wiz-uids="zJHMbe_b,zJHMbe_c" data-processed="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=zJHMbe_a/TKHnVd" data-processed="true"&gt;&lt;SPAN aria-hidden="true" data-processed="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV class="Fsg96" data-sfc-cp="" data-processed="true"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV class="otQkpb" role="heading" aria-level="3" data-animation-nesting="" data-sfc-cp="" data-processed="true"&gt;1. Register Reading Command in Linux&lt;SPAN class="uJ19be notranslate" data-wiz-uids="zJHMbe_m,zJHMbe_n" data-processed="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=zJHMbe_l/TKHnVd" data-processed="true"&gt;&lt;SPAN aria-hidden="true" data-processed="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAQQAA" data-processed="true"&gt;To read the register values of &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;flexcan0&lt;/CODE&gt; (or any peripheral) after Linux has booted, use the &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;devmem&lt;/CODE&gt; tool.&lt;SPAN class="uJ19be notranslate" data-wiz-uids="zJHMbe_s,zJHMbe_t" data-processed="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=zJHMbe_r/TKHnVd" data-processed="true"&gt;&lt;SPAN aria-hidden="true" data-processed="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;UL class="KsbFXc U6u95" data-processed="true"&gt;
&lt;LI data-hveid="CAUQAA" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;Command Format: &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;devmem &amp;lt;physical_address&amp;gt; &amp;lt;width&amp;gt;&lt;/CODE&gt;&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAUQAQ" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;Example (reading FLEXCAN0 MCR register): Assuming base address is &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;0x401B4000&lt;/CODE&gt;, and MCR offset is &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;0x00&lt;/CODE&gt;:&lt;/SPAN&gt;
&lt;DIV class="r1PmQe" data-wiz-uids="zJHMbe_15,zJHMbe_16,zJHMbe_17" data-hveid="CAUQAg" data-processed="true"&gt;
&lt;DIV data-processed="true"&gt;
&lt;DIV class="pHpOfb" data-animation-atomic="" data-processed="true"&gt;
&lt;DIV class="vVRw1d" data-processed="true"&gt;bash&lt;/DIV&gt;
&lt;DIV class="pCTyYe" dir="ltr" data-processed="true"&gt;
&lt;PRE data-processed="true"&gt;&lt;CODE data-processed="true"&gt;&lt;SPAN class="undefined" data-processed="true"&gt;devmem &lt;/SPAN&gt;&lt;SPAN class="tnfcCf" data-processed="true"&gt;0x401B4000&lt;/SPAN&gt; &lt;SPAN class="tnfcCf" data-processed="true"&gt;32&lt;/SPAN&gt;
&lt;/CODE&gt;&lt;/PRE&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/LI&gt;
&lt;LI data-hveid="CAUQBA" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;Alternative for dumping specific memory regions:&lt;/SPAN&gt;
&lt;DIV class="r1PmQe" data-wiz-uids="zJHMbe_1e,zJHMbe_1f,zJHMbe_1g" data-hveid="CAUQBQ" data-processed="true"&gt;
&lt;DIV data-processed="true"&gt;
&lt;DIV class="pHpOfb" data-animation-atomic="" data-processed="true"&gt;
&lt;DIV class="vVRw1d" data-processed="true"&gt;bash&lt;/DIV&gt;
&lt;DIV class="pCTyYe" dir="ltr" data-processed="true"&gt;
&lt;PRE data-processed="true"&gt;&lt;CODE data-processed="true"&gt;&lt;SPAN class="undefined" data-processed="true"&gt;cat /dev/mem | hexdump -C ...
&lt;/SPAN&gt;&lt;/CODE&gt;&lt;/PRE&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;SPAN class="uJ19be notranslate" data-wiz-uids="zJHMbe_1k,zJHMbe_1l" data-processed="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=zJHMbe_1j/TKHnVd" data-processed="true"&gt;&lt;SPAN aria-hidden="true" data-processed="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/LI&gt;
&lt;/UL&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAYQAA" data-processed="true"&gt;&lt;EM class="eujQNb" data-processed="true"&gt;Note: Ensure the clock for the module is enabled in Linux, otherwise &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;devmem&lt;/CODE&gt; might cause a bus error/hang.&lt;/EM&gt;&lt;SPAN class="uJ19be notranslate" data-wiz-uids="zJHMbe_1r,zJHMbe_1s" data-processed="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=zJHMbe_1q/TKHnVd" data-processed="true"&gt;&lt;SPAN aria-hidden="true" data-processed="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV class="Fsg96" data-sfc-cp="" data-processed="true"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV class="otQkpb" role="heading" aria-level="3" data-animation-nesting="" data-sfc-cp="" data-processed="true"&gt;2. PFE Firmware Loading Process&lt;/DIV&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAgQAA" data-processed="true"&gt;The PFE firmware is typically loaded by the Linux kernel &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;pfeng&lt;/CODE&gt; driver during startup.&lt;/DIV&gt;
&lt;UL class="KsbFXc U6u95" data-processed="true"&gt;
&lt;LI data-hveid="CAkQAA" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;Driver Source: &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;drivers/net/ethernet/nxp/pfe/&lt;/CODE&gt; in the kernel source.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAkQAQ" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;Firmware Files: Usually &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;s32g_pfe_class.fw&lt;/CODE&gt; and &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;s32g_pfe_util.fw&lt;/CODE&gt; found in &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;/lib/firmware/&lt;/CODE&gt;.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAkQAg" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;Key Functions: The loading process involves &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;pfe_firmware_load()&lt;/CODE&gt; and subsequent initialization routines in the PFE driver that send the FW to the PFE processor.&lt;/SPAN&gt;&lt;SPAN class="uJ19be notranslate" data-wiz-uids="zJHMbe_2k,zJHMbe_2l" data-processed="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=zJHMbe_2j/TKHnVd" data-processed="true"&gt;&lt;SPAN aria-hidden="true" data-processed="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/LI&gt;
&lt;/UL&gt;
&lt;DIV class="Fsg96" data-sfc-cp="" data-processed="true"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV class="otQkpb" role="heading" aria-level="3" data-animation-nesting="" data-sfc-cp="" data-processed="true"&gt;3. Changing HIL1 to HIL0&lt;/DIV&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAsQAA" data-processed="true"&gt;If you are using PFE-Master on the M7 core and need to change the High-Level Interface (HIL) to HIL0 (direct memory access) from HIL1 (often used in slave configurations), you need to modify the PFE driver initialization.&lt;SPAN class="uJ19be notranslate" data-wiz-uids="zJHMbe_2y,zJHMbe_2z" data-processed="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=zJHMbe_2x/TKHnVd" data-processed="true"&gt;&lt;SPAN aria-hidden="true" data-processed="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;UL class="KsbFXc U6u95" data-processed="true"&gt;
&lt;LI data-hveid="CAwQAA" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;File to modify: &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;pfe_module.c&lt;/CODE&gt; or similar PFE driver files in &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;drivers/net/ethernet/nxp/pfe/&lt;/CODE&gt;.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAwQAQ" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;Procedure:&lt;/SPAN&gt;
&lt;OL class="IaGLZe VimKh" data-processed="true"&gt;
&lt;LI data-hveid="CAwQAg" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;Locate the PFE driver code in the kernel source.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAwQAw" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;Find the initialization structures where the HIL mode is configured (look for &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;pfe_hil_mode&lt;/CODE&gt; or similar variables).&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAwQBA" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;Change the configuration from &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;1&lt;/CODE&gt; (HIL1) to &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;0&lt;/CODE&gt; (HIL0).&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAwQBQ" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;Recompile the PFE driver (&lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;pfeng.ko&lt;/CODE&gt; or built-in).&lt;/SPAN&gt;&lt;SPAN class="uJ19be notranslate" data-wiz-uids="zJHMbe_3n,zJHMbe_3o" data-processed="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=zJHMbe_3m/TKHnVd" data-processed="true"&gt;&lt;SPAN aria-hidden="true" data-processed="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/LI&gt;
&lt;/OL&gt;
&lt;/LI&gt;
&lt;/UL&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CA0QAA" data-processed="true"&gt;&lt;EM class="eujQNb" data-processed="true"&gt;Note: PFE-Master often runs on M7, and PFE-Slave on A53. If you run both, HIL settings must match.&lt;/EM&gt;&lt;SPAN class="uJ19be notranslate" data-wiz-uids="zJHMbe_3t,zJHMbe_3u" data-processed="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=zJHMbe_3s/TKHnVd" data-processed="true"&gt;&lt;SPAN aria-hidden="true" data-processed="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV class="Fsg96" data-sfc-cp="" data-processed="true"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV class="otQkpb" role="heading" aria-level="3" data-animation-nesting="" data-sfc-cp="" data-processed="true"&gt;Additional Troubleshooting Suggestions&lt;/DIV&gt;
&lt;UL class="KsbFXc U6u95" data-processed="true"&gt;
&lt;LI data-hveid="CBAQAA" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;Stop PFE in U-Boot: To verify the conflict, stop PFE in U-Boot before loading Linux using &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;pfeng stop&lt;/CODE&gt;.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CBAQAQ" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;Check Clock/Pin Conflict: PFE and FlexCAN can share clocks or have pin multiplexing conflicts. Check that the device tree on the A-core side does not enable PFE for the same resources used by M7.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CBAQAg" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;M7 Crash: If M7 crashes, check its memory region using &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;devmem&lt;/CODE&gt; to see if the M7 code still exists or if it has been overwritten.&lt;/SPAN&gt;&lt;SPAN class="uJ19be notranslate" data-wiz-uids="zJHMbe_50,zJHMbe_51" data-processed="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=zJHMbe_4z/TKHnVd" data-processed="true"&gt;&lt;SPAN aria-hidden="true" data-processed="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;&lt;SPAN class="uJ19be notranslate" data-wiz-uids="zJHMbe_50,zJHMbe_51" data-processed="true"&gt;Regards&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Mon, 16 Feb 2026 15:49:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Re-S32G274-Debugging-CAN-Communication-After-Dual-Core-Boot-up/m-p/2318649#M16029</guid>
      <dc:creator>Bio_TICFSL</dc:creator>
      <dc:date>2026-02-16T15:49:26Z</dc:date>
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