S32G中的主题 Re: s32g DDR change

s32g DDR change

ZHANGBOWEN — Mon, 02 Feb 2026 04:31:42 GMT

Hi, NXP expert

The chip used in my development board is S32G274A and bsp38. Currently, I want to change the ddr from the original 4GB to 2GB. I have configured the ddr through S32DS in accordance with the S32G memory configuration and test manual, verified and exported the ATF source code, as shown in the following figure.

Then, referring to the "S32G RDB2 Linux Board-level Development Kit ATF Customization" manual and the DDR modification section in "S32G RDB2 Linux Board-level Development Kit Uboot Customization", the corresponding ddr file has been replaced. Now there are several phenomena.

(1) when I'm not modify/home/ZBW/workspace/s32g/arm - trusted - the firmware - NXP/FDTS/s32g2 dtsi that maintain the contents of the memory node as shown below, when I find uboot can normal boot, However, starting the kernel will result in an error,and the error message is also posted in the following picture

error log:

=> boot switch to partitions #0, OK mmc0(part 0) is current device 18864640 bytes read in 234 ms (76.9 MiB/s) Booting from mmc ... 56397 bytes read in 10 ms (5.4 MiB/s) ## Flattened Device Tree blob at 83000000 Booting using the fdt blob at 0x83000000 Using Device Tree in place at 0000000083000000, end 0000000083010c4c fixup: pfe0 set to 00:01:be:be:ef:11 fixup: pfe0: Update fixed-link speed to 1000Mbps fixup: pfe1 set to 00:01:be:be:ef:22 fixup: pfe2 set to 00:01:be:be:ef:33 Starting kernel ... [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034] [ 0.000000] Linux version 5.15.119-rt65+gd6fac1c66 (oe-user@oe-host) (aarch64-fsl-linux-gcc (GCC) 11.3.0, GNU ld (GNU Binutils) 2.38.20220708) #1 SMP PREEMPT Thu Oct 30 12:05:44 CST 2025 [ 0.000000] Machine model: GRCE DOCAP-BAS [ 0.000000] earlycon: linflex0 at MMIO 0x00000000401c8000 (options '115200n8') [ 0.000000] printk: bootconsole [linflex0] enabled [ 0.000000] efi: UEFI not found. [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000083200000, size 3 MiB [ 0.000000] OF: reserved mem: initialized node pfebufs@83200000, compatible id shared-dma-pool [ 0.000000] Zone ranges: [ 0.000000] DMA [mem 0x0000000080000000-0x00000000ffffffff] [ 0.000000] DMA32 empty [ 0.000000] Normal [mem 0x0000000100000000-0x00000008ffffffff] [ 0.000000] Movable zone start for each node [ 0.000000] Early memory node ranges [ 0.000000] node 0: [mem 0x0000000080000000-0x00000000831fffff] [ 0.000000] node 0: [mem 0x0000000083200000-0x00000000835dffff] [ 0.000000] node 0: [mem 0x00000000835e0000-0x0000000083ffffff] [ 0.000000] node 0: [mem 0x0000000084000000-0x00000000843fffff] [ 0.000000] node 0: [mem 0x0000000084400000-0x0000000084ffffff] [ 0.000000] node 0: [mem 0x0000000085000000-0x0000000085000fff] [ 0.000000] node 0: [mem 0x0000000085001000-0x00000000bfffffff] [ 0.000000] node 0: [mem 0x00000000c0000000-0x00000000c07fffff] [ 0.000000] node 0: [mem 0x00000000c0800000-0x00000000cfffffff] [ 0.000000] node 0: [mem 0x00000000d0001000-0x00000000efffffff] [ 0.000000] node 0: [mem 0x0000000880000000-0x00000008ffffffff] [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x00000008ffffffff] [ 0.000000] On node 0, zone DMA: 1 pages in unavailable ranges [ 0.000000] cma: Reserved 256 MiB at 0x00000000e0000000 [ 0.000000] psci: probing for conduit method from DT.

(2) When I modified the device tree to comment out the memory@880000000 in the memory node, and then recompiled U-boot and burned it in, only one line of NOTICE: Reset status: Power-On Reset will be displayed

回复： s32g DDR change

ZHANGBOWEN — Mon, 02 Feb 2026 07:23:58 GMT

Supplementary information: DDR TOOL configuration diagram, and verified successfully

When I was in the first situation where I could enter U-Boot, I manually set the size of mem in the U-Boot command line

setenv mmcargs 'run finduuid;setenv bootargs console=${console},${baudrate} mem=2G root=PARTUUID=${uuid} rw rootfstype=${mmcrootfstype} earlycon nohz=off coherent_pool=64M'

The phenomenon is inconsistent

NOTICE: Reset status: Power-On Reset
NOTICE: BL2: v2.5(release):bsp38.0-2.5-dirty
NOTICE: BL2: Built : 06:47:45, Feb 2 2026
NOTICE: BL2: Booting BL31

U-Boot 2020.04-00006-g2560e070-dirty (Feb 02 2026 - 14:47:43 +0800)

SoC: NXP S32G274A rev. 2.0
CPU: ARM Cortex-A53 r0p4 @ max 1000 MHz
Model: NXP S32G274A-RDB2
DRAM: 3.8 GiB
MMC: FSL_SDHC: 0
Loading Environment from SPI Flash... SF: Detected mx25uw51245g with page size 256 Bytes, erase size 64 KiB, total 64 MiB
OK
Configuring PCIe0 as RootComplex
PCIe0: Link up! X1, Gen3
Device 'pcie@44100000': seq 1 is in use by 'pci_0:0.0'
Configuring PCIe1 as RootComplex
PCIe1: Failed to get link up
PCI: Failed autoconfig bar 20
PCI: Failed autoconfig bar 24
BusDevFun VendorId DeviceId Device Class Sub-Class
______________________________________________________________________
pcie@40400000 RootComplex
| `-- 00:00.00 0x1957 0x4002 Bridge device 0x04
| `-- 01:00.000x1e4b 0x1202 Mass storage controller 0x08
In: serial@401c8000
Out: serial@401c8000
Err: serial@401c8000
Board revision: RDB2/GLDBOX Revision D
Net: EQOS phy: rgmii @ 1

Warning: eth_eqos (eth0) using random MAC address - 12:ec:d2:dd:91:c8
eth0: eth_eqosFailed to get speed of XPCS for emac0_xpcs PFE: emac0: sgmii emac1: none emac2: rgmii
SF: Detected mx25uw51245g with page size 256 Bytes, erase size 64 KiB, total 64 MiB
## No elf image at address 0xefdc6a78
PFEng firmware file '<NULL>@0x03000000:<NULL>' loading failed: -22

cellular module power on
Hit any key to stop autoboot: 0
=>
=> printenv mmc
mmcargs mmcboot mmcdev mmcpart mmcroot mmcrootfstype
=> printenv mmcargs
mmcargs=run finduuid;setenv bootargs console=${console},${baudrate} root=PARTUUID=${uuid} rw rootfstype=${mmcrootfstype} earlycon nohz=off coherent_pool=64M
=> bdinfo
arch_number = 0x0000000000000000
boot_params = 0x0000000080000100
DRAM bank = 0x0000000000000000
-> start = 0x0000000080000000
-> size = 0x0000000070000000
DRAM bank = 0x0000000000000001
-> start = 0x0000000880000000
-> size = 0x0000000080000000
baudrate = 115200 bps
TLB addr = 0x00000000efff0000
relocaddr = 0x00000000efff0000
reloc off = 0x0000000000000000
irq_sp = 0x00000000efdc6b70
sp start = 0x00000000efdc6b70
Early malloc usage: 193d0 / 20000
fdt_blob = 0x00000000ffa97000
=> setenv mmcargs 'run finduuid;setenv bootargs console=${console},${baudrate} mem=2G root=PARTUUID=${uuid} rw rootfstype=${mmcrootfstype} earlycon nohz=off coherent_pool=64M'
=> boot
switch to partitions #0, OK
mmc0(part 0) is current device
18864640 bytes read in 234 ms (76.9 MiB/s)
Booting from mmc ...
56397 bytes read in 10 ms (5.4 MiB/s)
## Flattened Device Tree blob at 83000000
Booting using the fdt blob at 0x83000000
Using Device Tree in place at 0000000083000000, end 0000000083010c4c
fixup: pfe0 set to 00:01:be:be:ef:11
fixup: pfe0: Update fixed-link speed to 1000Mbps
fixup: pfe1 set to 00:01:be:be:ef:22
fixup: pfe2 set to 00:01:be:be:ef:33

Starting kernel ...

[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[ 0.000000] Linux version 5.15.119-rt65+gd6fac1c66 (oe-user@oe-host) (aarch64-fsl-linux-gcc (GCC) 11.3.0, GNU ld (GNU Binutils) 2.38.20220708) #1 SMP PREEMPT Thu Oct 30 12:05:44 CST 2025
[ 0.000000] Machine model: GRCE DOCAP-BAS
[ 0.000000] Memory limited to 2048MB
[ 0.000000] earlycon: linflex0 at MMIO 0x00000000401c8000 (options '115200n8')
[ 0.000000] printk: bootconsole [linflex0] enabled
[ 0.000000] efi: UEFI not found.
[ 0.000000] Reserved memory: created DMA memory pool at 0x0000000083200000, size 3 MiB
[ 0.000000] OF: reserved mem: initialized node pfebufs@83200000, compatible id shared-dma-pool
[ 0.000000] Zone ranges:
[ 0.000000] DMA [mem 0x0000000080000000-0x00000000ffffffff]
[ 0.000000] DMA32 empty
[ 0.000000] Normal [mem 0x0000000100000000-0x000000088fffffff]
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x0000000080000000-0x00000000831fffff]
[ 0.000000] node 0: [mem 0x0000000083200000-0x00000000835dffff]
[ 0.000000] node 0: [mem 0x00000000835e0000-0x0000000083ffffff]
[ 0.000000] node 0: [mem 0x0000000084000000-0x00000000843fffff]
[ 0.000000] node 0: [mem 0x0000000084400000-0x0000000084ffffff]
[ 0.000000] node 0: [mem 0x0000000085000000-0x0000000085000fff]
[ 0.000000] node 0: [mem 0x0000000085001000-0x00000000bfffffff]
[ 0.000000] node 0: [mem 0x00000000c0000000-0x00000000c07fffff]
[ 0.000000] node 0: [mem 0x00000000c0800000-0x00000000cfffffff]
[ 0.000000] node 0: [mem 0x00000000d0001000-0x00000000efffffff]
[ 0.000000] node 0: [mem 0x0000000880000000-0x000000088fffffff]
[ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000088fffffff]
[ 0.000000] On node 0, zone DMA: 1 pages in unavailable ranges
[ 0.000000] cma: Reserved 256 MiB at 0x00000000e0000000
[ 0.000000] psci: probing for conduit method from DT.
[ 0.000000] psci: PSCIv1.1 detected in firmware.
[ 0.000000] psci: Using standard PSCI v0.2 function IDs
[ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
[ 0.000000] psci: SMC Calling Convention v1.2
[ 0.000000] percpu: Embedded 27 pages/cpu s71000 r8192 d31400 u110592
[ 0.000000] pcpu-alloc: s71000 r8192 d31400 u110592 alloc=27*4096
[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3
[ 0.000000] SError Interrupt on CPU0, code 0x00000000bf000002 -- SError
[ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 5.15.119-rt65+gd6fac1c66 #1
[ 0.000000] Hardware name: GRCE DOCAP-BAS (DT)
[ 0.000000] pstate: 400000c5 (nZcv daIF -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[ 0.000000] pc : __next_mem_range_rev+0xd8/0x1fc
[ 0.000000] lr : __next_mem_range_rev+0x90/0x1fc
[ 0.000000] sp : ffffffc0090c3ab0
[ 0.000000] x29: ffffffc0090c3ab0 x28: 0000000000001000 x27: ffffffc00913e158
[ 0.000000] x26: 000000000000001c x25: ffffffc00913e130 x24: 0000000000000000
[ 0.000000] x23: ffffffc0090c3b70 x22: ffffffc0090c3b78 x21: 0000000000000000
[ 0.000000] x20: ffffffc0090c3b80 x19: ffffffc00913e158 x18: ffffffffffffffff
[ 0.000000] x17: 000000000000002c x16: 000000000001b000 x15: 0000000000000000
[ 0.000000] x14: 0000000000000018 x13: 000000000000000b x12: 00000000ffffffff
[ 0.000000] x11: 000000000000002c x10: 000000088fbb20a8 x9 : ffffffc00921f818
[ 0.000000] x8 : 000000000000001c x7 : 0000000880000000 x6 : 0000000890000000
[ 0.000000] x5 : 000000000000002c x4 : 000000000000001c x3 : 0000000000000000
[ 0.000000] x2 : 0000000000000000 x1 : ffffffc00921ea80 x0 : 0000000000000000
[ 0.000000] Kernel panic - not syncing:
[ 0.000000] Asynchronous SError Interrupt
[ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 5.15.119-rt65+gd6fac1c66 #1
[ 0.000000] Hardware name: GRCE DOCAP-BAS (DT)
[ 0.000000] Call trace:
[ 0.000000] dump_backtrace+0x0/0x1b0
[ 0.000000] show_stack+0x18/0x24
[ 0.000000] dump_stack_lvl+0x68/0x84
[ 0.000000] dump_stack+0x18/0x34
[ 0.000000] panic+0xb8/0x378
[ 0.000000] add_taint+0x0/0xc0
[ 0.000000] arm64_serror_panic+0x64/0x74
[ 0.000000] do_serror+0x58/0x60
[ 0.000000] el1h_64_error_handler+0x30/0x50
[ 0.000000] el1h_64_error+0x78/0x7c
[ 0.000000] __next_mem_range_rev+0xd8/0x1fc
[ 0.000000] memblock_find_in_range_node+0x228/0x240
[ 0.000000] memblock_alloc_range_nid+0xac/0x14c
[ 0.000000] memblock_alloc_internal+0x80/0xe0
[ 0.000000] memblock_alloc_try_nid+0xb8/0xe4
[ 0.000000] pcpu_alloc_first_chunk+0x13c/0x250
[ 0.000000] pcpu_setup_first_chunk+0x7d8/0x8c0
[ 0.000000] pcpu_embed_first_chunk+0x6c4/0x774
[ 0.000000] setup_per_cpu_areas+0x3c/0xc4
[ 0.000000] start_kernel+0x194/0x6bc
[ 0.000000] __primary_switched+0xa0/0xa8
[ 0.000000] Rebooting in 10 seconds..
NOTICE: Reset status: Destructive Reset (RUN)
NOTICE: BL2: v2.5(release):bsp38.0-2.5-dirty

Re: s32g DDR change

chenyin_h — Tue, 03 Feb 2026 02:12:59 GMT

Hello, @ZHANGBOWEN

Thanks for your post.

May I know if you had enabled ECC during the DDR tool configuration?

Chenyin

Re: s32g DDR change

ZHANGBOWEN — Tue, 03 Feb 2026 06:09:33 GMT

Hi, @chenyin_h

I have enabled ECC, Some of the configurations are shown in the following figure

Re: s32g DDR change

chenyin_h — Tue, 03 Feb 2026 10:38:52 GMT

Hello, @ZHANGBOWEN

Thanks for your reply.

When DDR ECC is enabled, the last 1/8 of the DDR capacity will be used to store ECC checksum values. Therefore, some changes may be needed to make the ECC-enabled DDR work normally.

1. Update the ATF configuration through the s32g_platform_def.h as follows.

#define BL33_BASE (S32G_DDR0_END - (256 * SIZE_1M) - S32G_BL33_IMAGE_SIZE - \

SIZE_1M + 1)

2. Follow the BSP UM to invoke menuconfig to set up the following specific configurations for U-Boot.

CONFIG_SYS_TEXT_BASE=0xefaa0000

CONFIG_SYS_DATA_BASE=0xefa00000

3. Comment out the 2nd memory mapping,

Then try rebuilding the TFA/uboot to test.

Chenyin

Re: s32g DDR change

ZHANGBOWEN — Tue, 03 Feb 2026 11:17:38 GMT

Hi @chenyin_h

Thanks for your reply.

According to your guidance,

for (1),

for (2)

for (3)

Did I understand and modify it correctly?

Then i rebuild the TFA/uboot to test, but the result is that only one line of NOTICE: Reset status: Power-On Reset is displayed

Re: s32g DDR change

ZHANGBOWEN — Wed, 04 Feb 2026 03:24:53 GMT

Hi, @chenyin_h

I just tested and found that when I disabled ECC, the system could get up and running normally.

So I want to know (1) if ECC is necessary and (2)what the impact will be if it is not enabled?

(3)If ECC is enabled, how should it be adaptively modified?

Re: s32g DDR change

chenyin_h — Wed, 04 Feb 2026 07:53:07 GMT

Hello, @ZHANGBOWEN

Thanks for your reply.

1 &2：

The function of DDR ECC is to detect and correct memory errors, it is usually used for highly reliable systems. Whether using ECC or not depends on your actual system requirements.

3. Sorry that there is not a formal patch for your case, since the default setup on RDB is 4G, I provided some tips that may help from the experience. let me continue checking on your issues.

Chenyin

Re: s32g DDR change

ZHANGBOWEN — Thu, 05 Feb 2026 01:12:25 GMT

Hi, @chenyin_h

Thanks for your reply.

If I want to enable ECC, are there any other ways to make the system start up normally?

Re: s32g DDR change

chenyin_h — Fri, 06 Feb 2026 06:46:22 GMT

Hello, @ZHANGBOWEN

Thanks for your reply.

I reviewed the parameters you used in DDR tool again, and additionally suggest modifying the following:

Configure the "number of DRAM banks" to "1" in u-boot menuconfig ->General setup.

Then rebuild the images to have another trial.

Chenyin

Re: s32g DDR change

ZHANGBOWEN — Fri, 06 Feb 2026 07:40:52 GMT

Hi, @chenyin_h

According to your guidance, I have made the following modifications

1. Update the ATF configuration through the s32g_platform_def.h as follows.

#define BL33_BASE (S32G_DDR0_END - (256 * SIZE_1M) - S32G_BL33_IMAGE_SIZE - \

SIZE_1M + 1)

2. Follow the BSP UM to invoke menuconfig to set up the following specific configurations for U-Boot.

CONFIG_SYS_TEXT_BASE=0xefaa0000

CONFIG_SYS_DATA_BASE=0xefa00000

3. Comment out the 2nd memory mapping,

4. Configure the "number of DRAM banks" to "1" in u-boot menuconfig ->General setup.

Then i rebuild uboot, but the result is also that only one line of NOTICE: Reset status: Power-On Reset is displayed

Re: s32g DDR change

chenyin_h — Mon, 09 Feb 2026 03:15:45 GMT

Hello, @ZHANGBOWEN

Thanks for your reply.

Would you mind adding debug option to the TFA(add "DEBUG=1" during building), and rebuild it to share more information for further debugging?

Chenyin