<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: S32G2/G3 DDR Initialization on Cortex - M7 in S32G</title>
    <link>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2246760#M15541</link>
    <description>&lt;P&gt;hi，&lt;SPAN&gt;arun_belamge&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Thank you for your reply.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Please try to set the DDR clock/partition in the below picture showing.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Joey_z_0-1763965335675.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/366921i628E9F7100AB2E9B/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Joey_z_0-1763965335675.png" alt="Joey_z_0-1763965335675.png" /&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Joey_z_1-1763965355813.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/366922i3AC24EB0DB001ACD/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Joey_z_1-1763965355813.png" alt="Joey_z_1-1763965355813.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Hope this can help you.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;BR&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Joey&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Mon, 24 Nov 2025 06:24:12 GMT</pubDate>
    <dc:creator>Joey_z</dc:creator>
    <dc:date>2025-11-24T06:24:12Z</dc:date>
    <item>
      <title>S32G2/G3 DDR Initialization on Cortex - M7</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2192254#M15348</link>
      <description>&lt;P&gt;Hello All.&lt;/P&gt;&lt;P&gt;I want to place a part of my code in the external DDR RAM i.e.,&amp;nbsp;&lt;SPAN&gt;ORIGIN = 0x80000000, LENGTH = 0x40000000 (1GB).&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;I am running a Baremetal application on the Cortex - M7 core.&amp;nbsp;&lt;/P&gt;&lt;P&gt;I am unable to figure out how to ddr_init() and how to use the DDR Config Tool provided in the S32DS 3.6.&lt;/P&gt;&lt;P&gt;There is no in detail documentation / training on the same.&lt;/P&gt;&lt;P&gt;Please guide me on how to enable the DDR memory for Cortex - M7 and the initialization for the same.&lt;/P&gt;&lt;P&gt;Thanks in advance.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;BR&lt;/P&gt;&lt;P&gt;Arun&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 24 Oct 2025 04:58:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2192254#M15348</guid>
      <dc:creator>arun_belamge</dc:creator>
      <dc:date>2025-10-24T04:58:17Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2/G3 DDR Initialization on Cortex - M7</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2192356#M15349</link>
      <description>&lt;P&gt;hi,&lt;SPAN&gt;arun_belamge&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;Thank you for contacting us.&lt;/P&gt;
&lt;P&gt;Could you share more information with us?&lt;/P&gt;
&lt;P&gt;Do you use the S32G2 or S32G3? Which version of RTD are you using?&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Joey&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 24 Oct 2025 07:36:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2192356#M15349</guid>
      <dc:creator>Joey_z</dc:creator>
      <dc:date>2025-10-24T07:36:19Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2/G3 DDR Initialization on Cortex - M7</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2192404#M15350</link>
      <description>&lt;P&gt;Hi Joey.&lt;/P&gt;&lt;P&gt;Thank you for the response.&lt;/P&gt;&lt;P&gt;Following are the details,&lt;/P&gt;&lt;P&gt;1. Board: S32G-VNP-RDB3 (S32G399A-RDB) (Primarily working on this)&lt;/P&gt;&lt;P&gt;2. Board:&amp;nbsp;S32G-PROCEVB3-S (S32G274A-EVB) (Will try on this as well)&lt;/P&gt;&lt;P&gt;3. S32DS v3.6.0&lt;/P&gt;&lt;P&gt;4. RTD:&amp;nbsp;&lt;SPAN&gt;S32_RTD_5_0_0_QLP03_D2505_ASR_REL_4_4_REV_0000_20250530&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;BR&lt;/P&gt;&lt;P&gt;Arun&lt;/P&gt;</description>
      <pubDate>Fri, 24 Oct 2025 08:37:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2192404#M15350</guid>
      <dc:creator>arun_belamge</dc:creator>
      <dc:date>2025-10-24T08:37:36Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2/G3 DDR Initialization on Cortex - M7</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2193100#M15355</link>
      <description>&lt;P&gt;Hi,&amp;nbsp;&lt;SPAN&gt;arun_belamge&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;Thank you for your reply.&lt;/P&gt;
&lt;P&gt;We have supported the similar question before; you can try to refer to this link:&amp;nbsp;&amp;nbsp;&lt;/P&gt;
&lt;P style="margin: 0in; font-family: Calibri; font-size: 11.0pt;"&gt;&lt;A href="https://community.nxp.com/t5/S32G/Initialization-LPDDR-on-M7-0-core-of-S32G2/td-p/1976037" target="_blank"&gt;Solved: Initialization LPDDR on M7_0 core of S32G2 - NXP Community&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;You can tell me if it has help with you. If you still need to help for this question, you can contact me any time.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Joey&lt;/P&gt;</description>
      <pubDate>Mon, 27 Oct 2025 02:46:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2193100#M15355</guid>
      <dc:creator>Joey_z</dc:creator>
      <dc:date>2025-10-27T02:46:26Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2/G3 DDR Initialization on Cortex - M7</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2194770#M15375</link>
      <description>&lt;P&gt;Hello Joey.&lt;/P&gt;&lt;P&gt;Is there anything similar for the S32G399A-RDB3 board?&lt;/P&gt;&lt;P&gt;Currently, I have to work on the G3 board and using the above Diagnostic package, I am only able to build S32G2 tests and not G3 tests.&lt;/P&gt;&lt;P&gt;If i try to copy the DDR APIs to my existing project, I am having issues with conflicting header files such as StandardTypes.h and StdTypes.h.&lt;/P&gt;&lt;P&gt;Is there any simple straight forward way to initialize DDR memory controller and place my code on it?&lt;/P&gt;&lt;P&gt;Thank you.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;BR&lt;/P&gt;&lt;P&gt;Arun&lt;/P&gt;</description>
      <pubDate>Wed, 29 Oct 2025 04:46:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2194770#M15375</guid>
      <dc:creator>arun_belamge</dc:creator>
      <dc:date>2025-10-29T04:46:14Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2/G3 DDR Initialization on Cortex - M7</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2195412#M15380</link>
      <description>&lt;P&gt;hi，&lt;SPAN&gt;arun_belamge&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;Sorry for that we do not have the direct guide for S32G3.&lt;/P&gt;
&lt;P&gt;You also can try to refer to s32g2 reference to create DDR code for using S32G3.&lt;/P&gt;
&lt;P&gt;Also, you can refer to the AN12848 to find more DDR information. About how to use the DDR Tool.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Joey_z_0-1761793736240.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/363154iB0C2DB63D9AA372E/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Joey_z_0-1761793736240.png" alt="Joey_z_0-1761793736240.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&lt;A href="https://www.nxp.com.cn/webapp/sps/download/preDownload.jsp?render=true" target="_blank"&gt;AN12848: DDR Initialization and calibration on the S32G2 Vehicle Network Processor Application Note&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;Hope this can help you.&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Joey&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 30 Oct 2025 03:10:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2195412#M15380</guid>
      <dc:creator>Joey_z</dc:creator>
      <dc:date>2025-10-30T03:10:31Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2/G3 DDR Initialization on Cortex - M7</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2198018#M15413</link>
      <description>&lt;P&gt;Hello Joey.&lt;/P&gt;&lt;P&gt;Sorry for the late response.&lt;/P&gt;&lt;P&gt;I compiled and built the Diagnostics CM7 test for S32G2 with the Linflexd_UART and LPDDR4 Tests enabled, disabling other tests.&lt;/P&gt;&lt;P&gt;After successfully building and creating the blob.bin for the SD card and flashing it, I am not able to see any logs/print on the console.&lt;/P&gt;&lt;P&gt;Can you please help?&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;&lt;P&gt;BR&lt;/P&gt;&lt;P&gt;Arun&lt;/P&gt;</description>
      <pubDate>Tue, 04 Nov 2025 06:12:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2198018#M15413</guid>
      <dc:creator>arun_belamge</dc:creator>
      <dc:date>2025-11-04T06:12:34Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2/G3 DDR Initialization on Cortex - M7</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2198617#M15420</link>
      <description>&lt;P&gt;hi，&lt;SPAN&gt;arun_belamge&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;Thank you for your reply.&lt;/P&gt;
&lt;P&gt;Could you share more information with me about apply the&amp;nbsp;blob.bin?&amp;nbsp;&lt;/P&gt;
&lt;P&gt;How do you create the blob.bin and set the load adderss?&lt;/P&gt;
&lt;P&gt;Also, do you have any debugger for this application? you can try to use the debugger to debug it and observe the UART output informaiton.&lt;/P&gt;
&lt;P&gt;Hope this can help you.&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Joey&lt;/P&gt;</description>
      <pubDate>Wed, 05 Nov 2025 01:58:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2198617#M15420</guid>
      <dc:creator>Joey_z</dc:creator>
      <dc:date>2025-11-05T01:58:51Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2/G3 DDR Initialization on Cortex - M7</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2198684#M15422</link>
      <description>&lt;P&gt;Hi Joey.&lt;/P&gt;&lt;P&gt;I followed the document,&amp;nbsp;S32G-VNP-EVBx Diagnostics (Document identifier: S32GVNPEVBXDGUG).&lt;/P&gt;&lt;P&gt;Using this, I created the blob.bin as follows:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="arun_belamge_0-1762314941982.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/364015i4128E1DDE3AD3592/image-size/medium?v=v2&amp;amp;px=400" role="button" title="arun_belamge_0-1762314941982.png" alt="arun_belamge_0-1762314941982.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;&lt;STRONG&gt;Set both RAM start pointer and RAM entry pointer to 0x34000000. This value comes from the value set in the linker file.&lt;/STRONG&gt;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;&lt;STRONG&gt;Set the Code length to 0x300000 and the Start address to 0x2000.&lt;/STRONG&gt;&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;And, No I do not have any debugger currently at my disposal.&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;BR&lt;/P&gt;&lt;P&gt;Arun&lt;/P&gt;</description>
      <pubDate>Wed, 05 Nov 2025 03:57:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2198684#M15422</guid>
      <dc:creator>arun_belamge</dc:creator>
      <dc:date>2025-11-05T03:57:30Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2/G3 DDR Initialization on Cortex - M7</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2198762#M15424</link>
      <description>&lt;P&gt;hi，&lt;SPAN&gt;arun_belamge&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;Could you try to use only the UART demo for the SD boot? It is the better way to check the issue if cause by boot step.&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Joey&lt;/P&gt;</description>
      <pubDate>Wed, 05 Nov 2025 06:28:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2198762#M15424</guid>
      <dc:creator>Joey_z</dc:creator>
      <dc:date>2025-11-05T06:28:04Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2/G3 DDR Initialization on Cortex - M7</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2198961#M15425</link>
      <description>&lt;P&gt;Hi Joey.&lt;/P&gt;&lt;P&gt;The UART demo also seems to not work on the G2 board.&lt;/P&gt;&lt;P&gt;I suspect, its the default Linflexd_UART_1 channel which is not present on the&amp;nbsp;&lt;STRONG&gt;S32G-PROCEVB-S processor board ONLY&lt;/STRONG&gt;. I do not have the evaluation board.&lt;/P&gt;&lt;P&gt;Please clarify, the UART present on the board is &lt;STRONG&gt;J58&lt;/STRONG&gt; and not J1 which is given in the example project.&lt;/P&gt;&lt;P&gt;If thats the case, how do I initialize the UART0, J58 and print on the console?&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;&lt;P&gt;BR&lt;/P&gt;</description>
      <pubDate>Wed, 05 Nov 2025 09:56:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2198961#M15425</guid>
      <dc:creator>arun_belamge</dc:creator>
      <dc:date>2025-11-05T09:56:49Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2/G3 DDR Initialization on Cortex - M7</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2199652#M15435</link>
      <description>&lt;P&gt;hi,&lt;SPAN&gt;arun_belamge&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;Thank you for your reply.&lt;/P&gt;
&lt;P&gt;The demo of&amp;nbsp;Linflexd_Uart_Ip_Example_S32G274A_M7 uses the RDB2 board.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Joey_z_0-1762396404671.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/364197i614DA83E4CD03EE8/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Joey_z_0-1762396404671.png" alt="Joey_z_0-1762396404671.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;And it uses the J1 for UART1 as the following picture.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Joey_z_1-1762396422450.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/364198i0566162C569D579F/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Joey_z_1-1762396422450.png" alt="Joey_z_1-1762396422450.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Joey_z_2-1762396434316.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/364199i4665AB57E7EA9AC9/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Joey_z_2-1762396434316.png" alt="Joey_z_2-1762396434316.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;Hope this can help you.&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Joey&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 06 Nov 2025 02:34:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2199652#M15435</guid>
      <dc:creator>Joey_z</dc:creator>
      <dc:date>2025-11-06T02:34:48Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2/G3 DDR Initialization on Cortex - M7</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2199698#M15436</link>
      <description>&lt;P&gt;Hi Joey.&lt;/P&gt;&lt;P&gt;Thanks for pointing it out.&lt;/P&gt;&lt;P&gt;But, in the diagnostic test project, LinflexD_UART_0 i.e., J58 is being used to print on the console.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="arun_belamge_0-1762400898045.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/364213i7DC6B57F6BF37EBF/image-size/medium?v=v2&amp;amp;px=400" role="button" title="arun_belamge_0-1762400898045.png" alt="arun_belamge_0-1762400898045.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;So, it should have worked...&lt;/P&gt;&lt;P&gt;Is the Baud rate:9600 or 27210884bps as given in the diagram?&lt;/P&gt;&lt;P&gt;Can i flash the app to QSPI flash instead of SD card?&lt;/P&gt;&lt;P&gt;Thank you.&lt;/P&gt;&lt;P&gt;BR&lt;/P&gt;&lt;P&gt;Arun&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 06 Nov 2025 03:50:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2199698#M15436</guid>
      <dc:creator>arun_belamge</dc:creator>
      <dc:date>2025-11-06T03:50:08Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2/G3 DDR Initialization on Cortex - M7</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2200432#M15442</link>
      <description>&lt;P&gt;hi,&lt;SPAN&gt;arun_belamge&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;Thank you for your reply.&lt;/P&gt;
&lt;P&gt;The diagnostic of your showing if for EVB board, and the RTD demo is for RBD board, so it has the different hardware setting.&lt;/P&gt;
&lt;P&gt;Yes, you can try to&amp;nbsp;flash the app to QSPI flash instead of SD card. You can try to refer to this link:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://www.nxp.com/document/guide/getting-started-with-the-s32g-reference-design-board-2-for-vehicle-network-processing:GS-S32G-VNP-RDB2" target="_blank" rel="noopener"&gt;Getting Started with the S32G Reference Design Board 2 for Vehicle Network Processing | NXP Semiconductors&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&lt;A href="https://www.nxp.com/document/guide/getting-started-with-the-s32g-evaluation-board-for-vehicle-network-processing:GS-S32G-VNP-EVB" target="_blank"&gt;Getting Started with the S32G Evaluation Board for Vehicle Network Processing | NXP Semiconductors&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Joey_z_0-1762481696975.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/364349iE7058F9F40DA64F4/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Joey_z_0-1762481696975.png" alt="Joey_z_0-1762481696975.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;Hope this can help you.&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Joey&lt;/P&gt;</description>
      <pubDate>Fri, 07 Nov 2025 02:16:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2200432#M15442</guid>
      <dc:creator>Joey_z</dc:creator>
      <dc:date>2025-11-07T02:16:13Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2/G3 DDR Initialization on Cortex - M7</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2217212#M15524</link>
      <description>&lt;P&gt;Hi Joey.&lt;/P&gt;&lt;P&gt;After switching to S32DS 3.5 and RTD 5.0, I was able to use the DDR Tool and generate the DDR board files.&lt;/P&gt;&lt;P&gt;After I update the code, I use &lt;EM&gt;&lt;STRONG&gt;ddr_init()&amp;nbsp;&lt;/STRONG&gt;&lt;/EM&gt;in my baremetal application, but when I run the program, it hangs / stops at the point where I have called ddr_init().&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="arun_belamge_0-1763612028004.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/366573i38E6F6F249D5C6D4/image-size/medium?v=v2&amp;amp;px=400" role="button" title="arun_belamge_0-1763612028004.png" alt="arun_belamge_0-1763612028004.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Defined ddr memory as, DDR0 (RWIX) : ORIGIN = 0x80000000 LENGTH = 0x40000000 (1gb), in linker.&lt;/P&gt;&lt;P&gt;Please help.&amp;nbsp;&lt;/P&gt;&lt;P&gt;P.S. I do not have any debugger at the moment.&lt;/P&gt;&lt;P&gt;Thank you.&lt;/P&gt;&lt;P&gt;BR&lt;/P&gt;&lt;P&gt;Arun&lt;/P&gt;</description>
      <pubDate>Thu, 20 Nov 2025 04:13:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2217212#M15524</guid>
      <dc:creator>arun_belamge</dc:creator>
      <dc:date>2025-11-20T04:13:59Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2/G3 DDR Initialization on Cortex - M7</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2218986#M15527</link>
      <description>&lt;P&gt;hi,&lt;SPAN&gt;arun_belamge&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;Thank you for your reply.&lt;/P&gt;
&lt;P&gt;Could you share your project with me in the internal system? It is helpful for your issue.&lt;/P&gt;
&lt;P&gt;You can post the new case following this link: &lt;A href="https://support.nxp.com" target="_blank"&gt;https://support.nxp.com&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Joey&lt;/P&gt;</description>
      <pubDate>Thu, 20 Nov 2025 09:19:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2218986#M15527</guid>
      <dc:creator>Joey_z</dc:creator>
      <dc:date>2025-11-20T09:19:50Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2/G3 DDR Initialization on Cortex - M7</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2219039#M15528</link>
      <description>Hi Joey.&lt;BR /&gt;Thanks for the response.&lt;BR /&gt;I have already created one, below are the details:&lt;BR /&gt;*Project: SoC Benchmarking&lt;BR /&gt;*Case: 00748732&lt;BR /&gt;*Subject: DDR Memory Initialization from Cortex - M7</description>
      <pubDate>Thu, 20 Nov 2025 09:24:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2219039#M15528</guid>
      <dc:creator>arun_belamge</dc:creator>
      <dc:date>2025-11-20T09:24:00Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2/G3 DDR Initialization on Cortex - M7</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2232732#M15533</link>
      <description>&lt;P&gt;Hi Joey.&lt;/P&gt;&lt;P&gt;In the document AN12848 I can see the following NOTE.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="arun_belamge_0-1763719176726.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/366789i4DC0069073253831/image-size/medium?v=v2&amp;amp;px=400" role="button" title="arun_belamge_0-1763719176726.png" alt="arun_belamge_0-1763719176726.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;Can you tell me how to enable DDR partition and set the DDR_CLK?&lt;/P&gt;&lt;P&gt;Thank you.&lt;/P&gt;&lt;P&gt;BR&lt;/P&gt;&lt;P&gt;Arun&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 21 Nov 2025 10:01:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2232732#M15533</guid>
      <dc:creator>arun_belamge</dc:creator>
      <dc:date>2025-11-21T10:01:16Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2/G3 DDR Initialization on Cortex - M7</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2246760#M15541</link>
      <description>&lt;P&gt;hi，&lt;SPAN&gt;arun_belamge&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Thank you for your reply.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Please try to set the DDR clock/partition in the below picture showing.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Joey_z_0-1763965335675.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/366921i628E9F7100AB2E9B/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Joey_z_0-1763965335675.png" alt="Joey_z_0-1763965335675.png" /&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Joey_z_1-1763965355813.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/366922i3AC24EB0DB001ACD/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Joey_z_1-1763965355813.png" alt="Joey_z_1-1763965355813.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Hope this can help you.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;BR&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Joey&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 24 Nov 2025 06:24:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2246760#M15541</guid>
      <dc:creator>Joey_z</dc:creator>
      <dc:date>2025-11-24T06:24:12Z</dc:date>
    </item>
    <item>
      <title>Re: S32G2/G3 DDR Initialization on Cortex - M7</title>
      <link>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2246762#M15542</link>
      <description>&lt;P&gt;Hello Joey.&lt;/P&gt;&lt;P&gt;I have done the same config using the Clock Tool&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="arun_belamge_0-1763965646926.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/366923i3F9E775ED6490D79/image-size/medium?v=v2&amp;amp;px=400" role="button" title="arun_belamge_0-1763965646926.png" alt="arun_belamge_0-1763965646926.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;But i am not using any MCAL, the app is baremetal, and ddr_init() in app doesn't work even after the ddr clock enabled.&lt;/P&gt;&lt;P&gt;Thank you.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;BR&lt;/P&gt;&lt;P&gt;Arun&lt;/P&gt;</description>
      <pubDate>Mon, 24 Nov 2025 06:28:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G2-G3-DDR-Initialization-on-Cortex-M7/m-p/2246762#M15542</guid>
      <dc:creator>arun_belamge</dc:creator>
      <dc:date>2025-11-24T06:28:45Z</dc:date>
    </item>
  </channel>
</rss>

