topic Re: PHY Port switching in S32G-VNP-RDB2 in S32G

PHY Port switching in S32G-VNP-RDB2

Atkinson — Wed, 17 Sep 2025 06:25:46 GMT

Hi,

I am facing up a Issue in SJA1110 Switch where 100BASE-T1 PHY when i am configuring it in AUTOMATIC Mode its switching to MASTER Mode when the END_DEVICE in SLAVE mode.

In another situation where END_DEVICE in MASTER Mode configured board to be in AUTOMATIC Mode interfacing the end device Board the board need to be switched to SLAVE mode but its not switching as Expected.

I have configured AUTOMATIC MODE its not switching to SLAVE but when i configure explicitly for SLAVE mode the END_DEVICE is working since its in MASTER. but this needs to be done it

What are the test cases can be conducted to identify what would be the root cause of the issue?
How can i check the register Values whether its switching MASTER/SLAVE or not ?
How can i resolve this issue !!

Regards
Atkinson

Re: PHY Port switching in S32G-VNP-RDB2

PavelL — Wed, 17 Sep 2025 08:08:48 GMT

Hello @Atkinson ,

Thank you for your report. Based on your description, it seems there is a misunderstanding regarding the meaning of PHY Role = Automatic in the context of the SJA1110 Automotive Ethernet switch.

In automotive applications, auto-negotiation is typically not used, because the roles (MASTER/SLAVE) are predefined and fixed during system design. Therefore, the "Automatic" setting does not imply dynamic negotiation. Instead, it means the PHY will follow the default configuration, which is usually determined by pin strapping.

Here is the definition of phy_role_t from the SJA1110 SDK 1.0.2 :

typedef enum
{
PHY_ROLE_AUTO = 2, /**< Automatic configuration, i.e. use the default of the device. Could be pin strapping or auto-negotiation of master/slave parameter. */
PHY_ROLE_MASTER = 1, /**< Master */
PHY_ROLE_SLAVE = 0 /**< Slave */
} phy_role_t;

To verify the current role of the PHY, please read the B100T1_PMA_CONTROL register, specifically bit 14, which indicates the MASTER/SLAVE status. Refer to UM11107 (Software user manual for SJA1110) for detailed register descriptions.

Please note: The MASTER/SLAVE setting is only relevant during the initial PHY link negotiation. After the link is established, both PHYs behave as equal peers, including support for features like TC10 sleep/wake signaling.

Best regards,

Pavel

Re: PHY Port switching in S32G-VNP-RDB2

Atkinson — Wed, 17 Sep 2025 09:28:46 GMT

Hi @PavelL

Thanks for the quick reply

so you are saying the AUTOMATIC setting will not reflect as MASTER / SLAVE depending on the end device which is getting connected at the port?

whether it is possible to make that reflect as MASTER/SLAVE switching when the device is getting interface if yes, how can we do that ?

When we are configuring the board to AUTOMATIC how can we make the pin strapping to switch to SLAVE because currently it switching to MASTER it' not switching to SLAVE whether this is a root cause or this is expected ?

Whether it will be possible to make when the configuration in AUTOMATIC if my END_DEVICE is coming up with MASTER the board is not able to switch to SLAVE but if my END_DEVICE is SLAVE and my board is able to switch to MASTER i am expecting to happen it for the opposite way also when the END_DEVICE in MASTER also the board is needed to switch to SLAVE

so, in order to make this, whether this is possible??

Regards
Atkinson

Re: PHY Port switching in S32G-VNP-RDB2

Atkinson — Thu, 18 Sep 2025 04:08:33 GMT

Hi @PavelL

So from your suggestion,

As you mentioned, Pin strapping will be happening during the startup process logic state of specific pins at power-on or reset. so, it will be setting up automatically the mode either MASTER / SLAVE
So i am seeing it's switching to MASTER but not to SLAVE in Board so how can i make that to switch to SLAVE also after the boot up, its able to switch to MASTER why it's not switching to SLAVE.
Its able to set MASTER in boot why its not making it SLAVE whether it is possible to make the pin strapping during the Power-ON / Reset.

Can you briefly give me steps to read the register which is setting MASTER/SLAVE
How can i do it in S32Design studio to read the register and check what bit it is setup

Re: PHY Port switching in S32G-VNP-RDB2

PavelL — Thu, 18 Sep 2025 07:24:00 GMT

Hello @Atkinson ,

Yes, you understood correctly — the "Automatic" setting does not dynamically switch between MASTER and SLAVE depending on the connected end device. Also, please note that auto-negotiation is not defined in the IEEE 802.3bw standard, which specifies 100BASE-T1. The MASTER/SLAVE roles must be preconfigured and are not negotiated dynamically. This is by design, to ensure deterministic link behavior in automotive environments.

If your board is switching to MASTER when configured as "Automatic", this is likely due to the pin strapping configuration or the default internal setting of the PHY. If you need the board to behave as SLAVE, you should explicitly configure the PHY role to SLAVE in software or adjust the pin strapping to reflect that.

To answer your question directly:

No, the PHY will not switch to SLAVE automatically when the end device is MASTER.
This behavior is expected, not a bug.
To make the board behave as SLAVE, you must either configure it explicitly in software (phy_role_t = PHY_ROLE_SLAVE) or change the pin strapping so that the default role becomes SLAVE.

If you want to change the default MASTER/SLAVE role used in "Automatic" mode, you have two options:

1. Software override: Set phy_role_t = PHY_ROLE_SLAVE explicitly in your board configuration. This bypasses the pin strapping.

2. Pin strapping adjustment: Modify the hardware configuration (pull-up/pull-down resistors on specific pins) to change the default role. Refer to the ah725720-AN13225 - SJA1110 Hardware Application Note(2.0), chapter 5.6 Pin strapping .

Best regards,

Pavel

Re: PHY Port switching in S32G-VNP-RDB2

Atkinson — Fri, 19 Sep 2025 06:55:18 GMT

Hi @PavelL

Thanks for sharing the more insights

So in order to check this
2. Pin strapping adjustment: Modify the hardware configuration (pull-up/pull-down resistors on specific pins) to change the default role. Refer to the ah725720-AN13225 - SJA1110 Hardware Application Note(2.0), chapter 5.6 Pin strapping

Base Address; port 5 = 19h port 6 = 20h, port 7 = 21h
can you give me the complete Address!!
and how can i make the default configuration to SLAVE

Where these changes need to be made can you be more specific

Regards
Atkinson

Re: PHY Port switching in S32G-VNP-RDB2

PavelL — Fri, 19 Sep 2025 10:07:21 GMT

Hello @Atkinson ,

Just to clarify - how are you accessing the SJA1110 switch in your setup?

Are you using the SPI_AP interface (i.e., external host MCU accessing the switch via SPI)?
Or is the configuration done internally, e.g., via the embedded Cortex-M7 core inside the switch?

In case of first option, the indirect addressing has been recently solved in this thread Solved: How to access SJA1110 100BASE-T1 PHY Clause45 register via SPI_AP - NXP Community

Here are examples for PHY5 and PHY6 master/slave settings:

        Write DEVICE_CONTROL: set CONFIG_ALL_ENABLE (0x0040) : 2000
spi_write 0x1C109E <- 0x0040
spi_write 0x1C10DE <- 0x2000

spi_write 0x1C1081 <- 0x0834
spi_read  0x1C10C1 =  0xC000
        Read B100T1_PMA_CONTROL (0x0834) sw0.phy5 : C000
        Write B100T1_PMA_CONTROL: set MASTER (0x0834) sw0.phy5 : 4000
spi_write 0x1C1081 <- 0x0834
spi_write 0x1C10C1 <- 0x4000
        Write B100T1_PMA_CONTROL: set SLAVE (0x0834) sw0.phy5 : 0000
spi_write 0x1C1081 <- 0x0834
spi_write 0x1C10C1 <- 0x0000

spi_write 0x1C1101 <- 0x0834
spi_read  0x1C1141 =  0x8000
        Read B100T1_PMA_CONTROL (0x0834) sw0.phy6 : 8000
        Write B100T1_PMA_CONTROL: set MASTER (0x0834) sw0.phy6 : 4000
spi_write 0x1C1101 <- 0x0834
spi_write 0x1C1141 <- 0x4000

        Write B100T1_PMA_CONTROL: set SLAVE (0x0834) sw0.phy6 : 0000
spi_write 0x1C1101 <- 0x0834
spi_write 0x1C1141 <- 0x0000

        Write DEVICE_CONTROL: reset CONFIG_ALL_ENABLE (0x0040) : 0000
spi_write 0x1C111E <- 0x0040
spi_write 0x1C115E <- 0x0000

Best regards,

Pavel