<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic S32 Customer Bootloader in S32G</title>
    <link>https://community.nxp.com/t5/S32G/S32-Customer-Bootloader/m-p/1531919#M1491</link>
    <description>&lt;P&gt;Anyone can explain the booting process ?&lt;/P&gt;&lt;P&gt;Can anyone look into below statement and correct if my understanding is wrong ?&lt;/P&gt;&lt;P&gt;Initially we need to select the Boot Mode using RCON or Fuse Configuration .&lt;/P&gt;&lt;P&gt;It will decide the location of IVT from where the Boot Manager is to be loaded.&lt;/P&gt;&lt;P&gt;If it's QSPI Load(Loading from NORFLASH) we need to place IVT at 0th Address, If it's any MMC device it should be at offset 0x1000.&lt;/P&gt;&lt;P&gt;The BootROM is the first sw that run after any reset.&lt;/P&gt;&lt;P&gt;It is placed in Internal ROM and is executed by M7 Core.&lt;/P&gt;&lt;P&gt;BootROM will load the IVT to SRAM (I need clarification of this) also since it contain location of the Bootmanager(BM) for M7 Core it will load that BM to SARM&amp;nbsp; and run it from SRAM.&lt;/P&gt;&lt;P&gt;This BM will help in the peripheral /clock initializations. Later BM of M7 will help to Copy the BM of A53 from NORFlash or EMMC devices to SRAM and run from SRAM.&lt;/P&gt;&lt;P&gt;Later this will help to Copy the Customer Application or Linux to SRAM or DDR and will pass control to the Application .&lt;/P&gt;&lt;P&gt;Then Application began execution . After a Power ON Reset&amp;nbsp; , the control directly comes to application only.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Please correct me if I'm wrong regarding the about flow.&amp;nbsp;&lt;/P&gt;&lt;P&gt;NXP documents wasn't giving me a clear picture regarding the same .&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;(mainly regarding&lt;/P&gt;&lt;P&gt;&amp;gt; where the IVT will be copied by BootROM ? without peripheral init. how the copy of the to external memory take place (since SRAM is external for S32G2) ?&lt;/P&gt;&lt;P&gt;&amp;gt; Will BootManager for M7 will copy to SRAM by BootROM&amp;nbsp; only ?&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;gt;Will peripheral init. clock init take place with the help of BM only?&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;gt; After Power on reset where the control will go if the program is currently running in application ? Should it follow the boot process again ? )&lt;/P&gt;</description>
    <pubDate>Tue, 04 Oct 2022 05:40:39 GMT</pubDate>
    <dc:creator>NP1</dc:creator>
    <dc:date>2022-10-04T05:40:39Z</dc:date>
    <item>
      <title>S32 Customer Bootloader</title>
      <link>https://community.nxp.com/t5/S32G/S32-Customer-Bootloader/m-p/1531919#M1491</link>
      <description>&lt;P&gt;Anyone can explain the booting process ?&lt;/P&gt;&lt;P&gt;Can anyone look into below statement and correct if my understanding is wrong ?&lt;/P&gt;&lt;P&gt;Initially we need to select the Boot Mode using RCON or Fuse Configuration .&lt;/P&gt;&lt;P&gt;It will decide the location of IVT from where the Boot Manager is to be loaded.&lt;/P&gt;&lt;P&gt;If it's QSPI Load(Loading from NORFLASH) we need to place IVT at 0th Address, If it's any MMC device it should be at offset 0x1000.&lt;/P&gt;&lt;P&gt;The BootROM is the first sw that run after any reset.&lt;/P&gt;&lt;P&gt;It is placed in Internal ROM and is executed by M7 Core.&lt;/P&gt;&lt;P&gt;BootROM will load the IVT to SRAM (I need clarification of this) also since it contain location of the Bootmanager(BM) for M7 Core it will load that BM to SARM&amp;nbsp; and run it from SRAM.&lt;/P&gt;&lt;P&gt;This BM will help in the peripheral /clock initializations. Later BM of M7 will help to Copy the BM of A53 from NORFlash or EMMC devices to SRAM and run from SRAM.&lt;/P&gt;&lt;P&gt;Later this will help to Copy the Customer Application or Linux to SRAM or DDR and will pass control to the Application .&lt;/P&gt;&lt;P&gt;Then Application began execution . After a Power ON Reset&amp;nbsp; , the control directly comes to application only.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Please correct me if I'm wrong regarding the about flow.&amp;nbsp;&lt;/P&gt;&lt;P&gt;NXP documents wasn't giving me a clear picture regarding the same .&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;(mainly regarding&lt;/P&gt;&lt;P&gt;&amp;gt; where the IVT will be copied by BootROM ? without peripheral init. how the copy of the to external memory take place (since SRAM is external for S32G2) ?&lt;/P&gt;&lt;P&gt;&amp;gt; Will BootManager for M7 will copy to SRAM by BootROM&amp;nbsp; only ?&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;gt;Will peripheral init. clock init take place with the help of BM only?&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;gt; After Power on reset where the control will go if the program is currently running in application ? Should it follow the boot process again ? )&lt;/P&gt;</description>
      <pubDate>Tue, 04 Oct 2022 05:40:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32-Customer-Bootloader/m-p/1531919#M1491</guid>
      <dc:creator>NP1</dc:creator>
      <dc:date>2022-10-04T05:40:39Z</dc:date>
    </item>
    <item>
      <title>Re: S32 Customer Bootloader</title>
      <link>https://community.nxp.com/t5/S32G/S32-Customer-Bootloader/m-p/1532151#M1495</link>
      <description>&lt;P&gt;Hello NP1,&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Typically for a S32G virgin device, the device must be setup to Serial Boot mode.&lt;/SPAN&gt;&lt;BR role="presentation" /&gt;&lt;SPAN&gt;Key steps for booting up the device:&lt;/SPAN&gt;&lt;BR role="presentation" /&gt;&lt;SPAN&gt;1.&lt;/SPAN&gt; &lt;SPAN&gt;Ensure power supply on the board&lt;/SPAN&gt;&lt;BR role="presentation" /&gt;&lt;SPAN&gt;2.&lt;/SPAN&gt; &lt;SPAN aria-owns="pdfjs_internal_id_52R"&gt;Ensure correct BMODE settings (set to Serial boot if setting A or D as explained below, follow Table 1)&lt;/SPAN&gt;&lt;BR role="presentation" /&gt;&lt;SPAN&gt;3.&lt;/SPAN&gt; &lt;SPAN&gt;Lauterbach (LTB) and T32 support for S32G&lt;/SPAN&gt;&lt;BR role="presentation" /&gt;&lt;SPAN&gt;4.&lt;/SPAN&gt; &lt;SPAN&gt;Steps in case BootROM is kept in serial mode and direct application is required to be run on CM7_0:&lt;/SPAN&gt;&lt;BR role="presentation" /&gt;&lt;SPAN&gt;a.&lt;/SPAN&gt; &lt;SPAN&gt;T32 Script to attach to S32G CM7_0&lt;/SPAN&gt;&lt;BR role="presentation" /&gt;&lt;SPAN&gt;b.&lt;/SPAN&gt; &lt;SPAN&gt;Small application (constraint – SRAM size of 8M)&lt;/SPAN&gt;&lt;BR role="presentation" /&gt;&lt;SPAN&gt;c.&lt;/SPAN&gt; &lt;SPAN&gt;T32 Script to configure and enable the CM7_0&lt;/SPAN&gt;&lt;BR role="presentation" /&gt;&lt;SPAN&gt;5.&lt;/SPAN&gt; &lt;SPAN&gt;Steps if Serial boot required:&lt;/SPAN&gt;&lt;BR role="presentation" /&gt;&lt;SPAN&gt;a.&lt;/SPAN&gt; &lt;SPAN&gt;Application binary to download (Constraint – SRAM size of 8K)&lt;/SPAN&gt;&lt;BR role="presentation" /&gt;&lt;SPAN&gt;b.&lt;/SPAN&gt; &lt;SPAN&gt;Tool to transfer binary on Serial (UART/CAN/ETHERNET) port&lt;/SPAN&gt;&lt;BR role="presentation" /&gt;&lt;SPAN&gt;c.&lt;/SPAN&gt; &lt;SPAN&gt;Hardware bus connection for the serial interface to S32GEVB&lt;/SPAN&gt;&lt;BR role="presentation" /&gt;&lt;SPAN&gt;6.&lt;/SPAN&gt; &lt;SPAN&gt;Steps if required boot from QSPI:&lt;/SPAN&gt;&lt;BR role="presentation" /&gt;&lt;SPAN&gt;a.&lt;/SPAN&gt; &lt;SPAN aria-owns="pdfjs_internal_id_53R"&gt;Configure BMODE to ‘10’ &lt;/SPAN&gt;&lt;BR role="presentation" /&gt;&lt;SPAN&gt;b.&lt;/SPAN&gt; &lt;SPAN&gt;Scripts to program QSPI flash&lt;/SPAN&gt;&lt;BR role="presentation" /&gt;&lt;SPAN&gt;7.&lt;/SPAN&gt; &lt;SPAN&gt;Steps if required boot from SD/MMC:&lt;/SPAN&gt;&lt;BR role="presentation" /&gt;&lt;SPAN&gt;a.&lt;/SPAN&gt; &lt;SPAN aria-owns="pdfjs_internal_id_54R"&gt;Configure BMODE to ‘10’&lt;/SPAN&gt;&lt;BR role="presentation" /&gt;&lt;SPAN&gt;b.&lt;/SPAN&gt; &lt;SPAN&gt;Scripts/Tools to program SD/MMC&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;And boot!!!&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;Regards&lt;/P&gt;</description>
      <pubDate>Tue, 04 Oct 2022 13:48:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32-Customer-Bootloader/m-p/1532151#M1495</guid>
      <dc:creator>Bio_TICFSL</dc:creator>
      <dc:date>2022-10-04T13:48:08Z</dc:date>
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  </channel>
</rss>

