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    <title>S32GのトピックS32G SerSes PFE SMGII Config</title>
    <link>https://community.nxp.com/t5/S32G/S32G-SerSes-PFE-SMGII-Config/m-p/2147681#M14453</link>
    <description>&lt;P&gt;&lt;SPAN&gt;Dear Engineers&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I am using S 3 2 G 3 9 9 A and referencing R D B 3 for design. Currently, I would like to configure the S e r d e s as follows.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="liuchi_0-1754488159787.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/351191iBEDF082BED9AA7C2/image-size/medium?v=v2&amp;amp;px=400" role="button" title="liuchi_0-1754488159787.png" alt="liuchi_0-1754488159787.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Wed, 06 Aug 2025 13:51:35 GMT</pubDate>
    <dc:creator>liuchi</dc:creator>
    <dc:date>2025-08-06T13:51:35Z</dc:date>
    <item>
      <title>S32G SerSes PFE SMGII Config</title>
      <link>https://community.nxp.com/t5/S32G/S32G-SerSes-PFE-SMGII-Config/m-p/2147681#M14453</link>
      <description>&lt;P&gt;&lt;SPAN&gt;Dear Engineers&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I am using S 3 2 G 3 9 9 A and referencing R D B 3 for design. Currently, I would like to configure the S e r d e s as follows.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="liuchi_0-1754488159787.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/351191iBEDF082BED9AA7C2/image-size/medium?v=v2&amp;amp;px=400" role="button" title="liuchi_0-1754488159787.png" alt="liuchi_0-1754488159787.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 06 Aug 2025 13:51:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G-SerSes-PFE-SMGII-Config/m-p/2147681#M14453</guid>
      <dc:creator>liuchi</dc:creator>
      <dc:date>2025-08-06T13:51:35Z</dc:date>
    </item>
    <item>
      <title>Re: S32G SerSes PFE SMGII Config</title>
      <link>https://community.nxp.com/t5/S32G/S32G-SerSes-PFE-SMGII-Config/m-p/2147961#M14458</link>
      <description>&lt;P&gt;Hello,&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/179571"&gt;@liuchi&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks for your post.&lt;/P&gt;
&lt;P&gt;1 For both boards, what are the working modes on serdes1? both are mode3?&lt;/P&gt;
&lt;P&gt;2. Which BSP you are working with?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Chenyin&lt;/P&gt;</description>
      <pubDate>Thu, 07 Aug 2025 02:30:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G-SerSes-PFE-SMGII-Config/m-p/2147961#M14458</guid>
      <dc:creator>chenyin_h</dc:creator>
      <dc:date>2025-08-07T02:30:18Z</dc:date>
    </item>
    <item>
      <title>Re: S32G SerSes PFE SMGII Config</title>
      <link>https://community.nxp.com/t5/S32G/S32G-SerSes-PFE-SMGII-Config/m-p/2147977#M14459</link>
      <description>&lt;P&gt;1. S e r D e s 0 working mode 2, S e r D e s 1 working mode 3&lt;BR /&gt;2.B S P 4 3。&lt;BR /&gt;The issue has now been resolved by fixing the S e r D e s 0&amp;nbsp; &amp;nbsp;L a n 1&amp;nbsp; rate in the device tree and removing the M D I O configuration. thank you!&lt;/P&gt;</description>
      <pubDate>Thu, 07 Aug 2025 02:48:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G-SerSes-PFE-SMGII-Config/m-p/2147977#M14459</guid>
      <dc:creator>liuchi</dc:creator>
      <dc:date>2025-08-07T02:48:06Z</dc:date>
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