topic S32G274A-M7 DTCM and Cache interaction in S32G

S32G274A-M7 DTCM and Cache interaction

nakrachi — Thu, 17 Jul 2025 23:30:26 GMT

Hello,

I'm investigating a strange bug that makes some function calls on the M7 core to spike from ~3us to up to 2ms (according to the measurements using the tracing module)

I disabled Data Cache (for testing) and it seems to make the issue go away, which got me thinking this might be a cache coherency issue ?

After digging a little bit more I noticed that the DTCM is used as a stack for each of the M7 cores, and the MPU region for it was set as cacheable - bufferable , which I think should not be the case ? I disabled the cache in the MPU entry, when I did that I started getting alignment exceptions (all from DTCM).

My question is, why cache as an effect on DTCM even if they are not sharing the same bus ?

Why having the DTCM MPU region set as cache-on masks the unaligned access errors ?

Also is it okay to use the DTCM for the stack? as GCC generates unaligned access instructions to the TCM memory.

Thank you

Re: S32G274A-M7 DTCM and Cache interaction

Joey_z — Fri, 18 Jul 2025 10:37:41 GMT

hi,nakrachi

Thank you for your question.

are you using the S32G2 on the multi-core? Do you use any demo and code for testing?

Could you share more information for us?

Joey

Re: S32G274A-M7 DTCM and Cache interaction

nakrachi — Fri, 18 Jul 2025 11:27:48 GMT

Hi Joey!

I am using the S32G2 in multi-core, the A53 are running Linux, and the M7 have a custom baremetal running on them.

Unfortunately I cannot share the code, but I can try to explain in detail what I am noticing.

The MPU entry for the DTCM was "mistakenly" set to cacheable, when I did set it to cacheable I started seeing unaligned access exceptions, after looking into the assembly, GCC was indeed generating unaligned word access on the DTCM (used as stack).

I then added -mno-unaligned-access to my gcc options and now I can set the DTCM MPU region to uncacheable without generating any exceptions.

It also seems to solve the bug I was after, trace data showed no spikes in function execution time.

But I am still puzzled by the effect of cache on the DTCM,

Why having the MPU region set to cacheable "masks" the unaligned access exceptions ?
Why disabling the cache, while keeping the MPU region as cacheable does not generate unaligned exceptions? and also as side effect, solve the execution time spikes?

Re: S32G274A-M7 DTCM and Cache interaction

Joey_z — Tue, 22 Jul 2025 02:39:54 GMT

hi, nakrachi

Thank you for your reply.

I'm glad to hear that your problem has been solved. This issue should be caused by incompatibility between the MCU and MPU in setting the DTCM area.

Joey