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    <title>topic 回复： Core1 Not Starting on S32DS399 Multi-Core System with UDE Debug in S32G</title>
    <link>https://community.nxp.com/t5/S32G/Core1-Not-Starting-on-S32DS399-Multi-Core-System-with-UDE-Debug/m-p/2114997#M13705</link>
    <description>&lt;P&gt;hi NXP Support Experts&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I'd like to add one more point: the multi-core license is already installed. I have verified this.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Could you please provide me with a demo showing how to start Core 1, Core 2, and Core 3 from Core 0?&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;It would be greatly appreciated if you could guide me on how to modify the UDE script to enter the reset handler for Core 1, Core 2, and Core 3.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Best Regards&lt;/P&gt;&lt;P&gt;Sandy Li&lt;/P&gt;</description>
    <pubDate>Thu, 12 Jun 2025 05:28:49 GMT</pubDate>
    <dc:creator>xlfd_1981</dc:creator>
    <dc:date>2025-06-12T05:28:49Z</dc:date>
    <item>
      <title>Core1 Not Starting on S32DS399 Multi-Core System with UDE Debug</title>
      <link>https://community.nxp.com/t5/S32G/Core1-Not-Starting-on-S32DS399-Multi-Core-System-with-UDE-Debug/m-p/2114424#M13689</link>
      <description>&lt;PRE&gt;Dear NXP Support Team,

&lt;SPAN&gt;I hope &lt;/SPAN&gt;&lt;SPAN&gt;this&lt;/SPAN&gt;&lt;SPAN&gt; message finds you well.&lt;/SPAN&gt;
&lt;SPAN&gt;I am currently working on a multi-&lt;/SPAN&gt;&lt;SPAN class=""&gt;core application on the NXP S32DS399 device &lt;/SPAN&gt;&lt;SPAN class=""&gt;using&lt;/SPAN&gt; &lt;SPAN class=""&gt;UDE&lt;/SPAN&gt; &lt;SPAN class=""&gt;(Universal Debug Engine)&lt;/SPAN&gt; &lt;SPAN class=""&gt;for&lt;/SPAN&gt;&lt;SPAN class=""&gt; debugging &lt;/SPAN&gt;&lt;SPAN class=""&gt;and&lt;/SPAN&gt;&lt;SPAN class=""&gt; flashing. I have encountered an issue where only Core0 is entering its reset handler after system reset, &lt;/SPAN&gt;&lt;SPAN class=""&gt;while&lt;/SPAN&gt;&lt;SPAN class=""&gt; Core1 does &lt;/SPAN&gt;&lt;SPAN class=""&gt;not&lt;/SPAN&gt;&lt;SPAN class=""&gt; seem to start at all.&lt;/SPAN&gt;
&lt;SPAN class=""&gt;Here are the details of my setup &lt;/SPAN&gt;&lt;SPAN class=""&gt;and&lt;/SPAN&gt;&lt;SPAN class=""&gt; observations:&lt;/SPAN&gt;
&lt;SPAN class=""&gt;- Device: NXP S32DS399&lt;/SPAN&gt;&lt;SPAN class=""&gt;- IDE/Debugger: PLS &lt;/SPAN&gt;&lt;SPAN class=""&gt;UDE&lt;/SPAN&gt; &lt;SPAN class=""&gt;(Universal Debug Engine)&lt;/SPAN&gt;
&lt;SPAN class=""&gt;- Cores: Cortex-M7 &lt;/SPAN&gt;&lt;SPAN class=""&gt;x4&lt;/SPAN&gt; &lt;SPAN class=""&gt;(Core0 ~ Core3)&lt;/SPAN&gt;
&lt;SPAN class=""&gt;- Issue: After reset, only Core0 enters its reset &lt;/SPAN&gt;&lt;SPAN class=""&gt;handler&lt;/SPAN&gt; &lt;SPAN class=""&gt;(`reset_handler`)&lt;/SPAN&gt;&lt;SPAN class=""&gt;, but Core1 does &lt;/SPAN&gt;&lt;SPAN class=""&gt;not&lt;/SPAN&gt;&lt;SPAN class=""&gt; appear to execute any code.&lt;/SPAN&gt;
&lt;SPAN class=""&gt;What I have tried so far:&lt;/SPAN&gt;&lt;SPAN class=""&gt;- Verified that the ELF file &lt;/SPAN&gt;&lt;SPAN class=""&gt;for&lt;/SPAN&gt;&lt;SPAN class=""&gt; Core1 is correctly loaded into memory via UDE's Memory Browser.&lt;/SPAN&gt;&lt;SPAN class=""&gt;- Attempted manual PC/SP setup in UDE &lt;/SPAN&gt;&lt;SPAN class=""&gt;for&lt;/SPAN&gt;&lt;SPAN class=""&gt; Core1 &lt;/SPAN&gt;&lt;SPAN class=""&gt;and&lt;/SPAN&gt;&lt;SPAN class=""&gt; resumed execution, but no response.&lt;/SPAN&gt;&lt;SPAN class=""&gt;- Checked the linker script &lt;/SPAN&gt;&lt;SPAN class=""&gt;for&lt;/SPAN&gt;&lt;SPAN class=""&gt; Core1 — it defines a valid &lt;/SPAN&gt;&lt;SPAN class=""&gt;vector&lt;/SPAN&gt;&lt;SPAN class=""&gt; table &lt;/SPAN&gt;&lt;SPAN class=""&gt;and&lt;/SPAN&gt;&lt;SPAN class=""&gt; entry point.&lt;/SPAN&gt;&lt;SPAN class=""&gt;- Suspect that there may be a hardware-level configuration &lt;/SPAN&gt;&lt;SPAN class=""&gt;required&lt;/SPAN&gt; &lt;SPAN class=""&gt;(e.g., &lt;/SPAN&gt;&lt;SPAN class=""&gt;register&lt;/SPAN&gt;&lt;SPAN class=""&gt; settings &lt;/SPAN&gt;&lt;SPAN class=""&gt;or&lt;/SPAN&gt;&lt;SPAN class=""&gt; core release mechanism)&lt;/SPAN&gt;&lt;SPAN class=""&gt; to allow Core1 to start executing after reset.&lt;/SPAN&gt;
&lt;SPAN class=""&gt;Could you please help me with the following?&lt;/SPAN&gt;
&lt;SPAN class=""&gt;1. What are the necessary steps to properly initialize &lt;/SPAN&gt;&lt;SPAN class=""&gt;and&lt;/SPAN&gt;&lt;SPAN class=""&gt; start Core1 on the S32DS399?&lt;/SPAN&gt;&lt;SPAN class=""&gt;2. Is there a specific &lt;/SPAN&gt;&lt;SPAN class=""&gt;register&lt;/SPAN&gt; &lt;SPAN class=""&gt;or&lt;/SPAN&gt; &lt;SPAN class=""&gt;module&lt;/SPAN&gt; &lt;SPAN class=""&gt;(e.g., MU, RCRU, etc.)&lt;/SPAN&gt;&lt;SPAN class=""&gt; that needs to be configured to "release" Core1 from reset?&lt;/SPAN&gt;&lt;SPAN class=""&gt;3. Do you have any example code &lt;/SPAN&gt;&lt;SPAN class=""&gt;or&lt;/SPAN&gt;&lt;SPAN class=""&gt; documentation showing how to boot multiple cores on &lt;/SPAN&gt;&lt;SPAN class=""&gt;this&lt;/SPAN&gt;&lt;SPAN class=""&gt; platform?&lt;/SPAN&gt;&lt;SPAN class=""&gt;4. Are there any known issues &lt;/SPAN&gt;&lt;SPAN class=""&gt;or&lt;/SPAN&gt;&lt;SPAN class=""&gt; limitations when &lt;/SPAN&gt;&lt;SPAN class=""&gt;using&lt;/SPAN&gt;&lt;SPAN class=""&gt; UDE &lt;/SPAN&gt;&lt;SPAN class=""&gt;for&lt;/SPAN&gt;&lt;SPAN class=""&gt; multi-core debugging &lt;/SPAN&gt;&lt;SPAN class=""&gt;and&lt;/SPAN&gt;&lt;SPAN class=""&gt; flashing on &lt;/SPAN&gt;&lt;SPAN class=""&gt;this&lt;/SPAN&gt;&lt;SPAN class=""&gt; device?&lt;/SPAN&gt;
&lt;SPAN class=""&gt;Any guidance &lt;/SPAN&gt;&lt;SPAN class=""&gt;or&lt;/SPAN&gt;&lt;SPAN class=""&gt; reference materials would be greatly appreciated.&lt;/SPAN&gt;
&lt;SPAN class=""&gt;Thank you very much &lt;/SPAN&gt;&lt;SPAN class=""&gt;for&lt;/SPAN&gt;&lt;SPAN class=""&gt; your support!&lt;/SPAN&gt;&lt;/PRE&gt;</description>
      <pubDate>Wed, 11 Jun 2025 10:46:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Core1-Not-Starting-on-S32DS399-Multi-Core-System-with-UDE-Debug/m-p/2114424#M13689</guid>
      <dc:creator>xlfd_1981</dc:creator>
      <dc:date>2025-06-11T10:46:33Z</dc:date>
    </item>
    <item>
      <title>回复： Core1 Not Starting on S32DS399 Multi-Core System with UDE Debug</title>
      <link>https://community.nxp.com/t5/S32G/Core1-Not-Starting-on-S32DS399-Multi-Core-System-with-UDE-Debug/m-p/2114997#M13705</link>
      <description>&lt;P&gt;hi NXP Support Experts&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I'd like to add one more point: the multi-core license is already installed. I have verified this.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Could you please provide me with a demo showing how to start Core 1, Core 2, and Core 3 from Core 0?&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;It would be greatly appreciated if you could guide me on how to modify the UDE script to enter the reset handler for Core 1, Core 2, and Core 3.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Best Regards&lt;/P&gt;&lt;P&gt;Sandy Li&lt;/P&gt;</description>
      <pubDate>Thu, 12 Jun 2025 05:28:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Core1-Not-Starting-on-S32DS399-Multi-Core-System-with-UDE-Debug/m-p/2114997#M13705</guid>
      <dc:creator>xlfd_1981</dc:creator>
      <dc:date>2025-06-12T05:28:49Z</dc:date>
    </item>
    <item>
      <title>回复： Core1 Not Starting on S32DS399 Multi-Core System with UDE Debug</title>
      <link>https://community.nxp.com/t5/S32G/Core1-Not-Starting-on-S32DS399-Multi-Core-System-with-UDE-Debug/m-p/2115626#M13720</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/235263"&gt;@xlfd_1981&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;For Multicore applications you need to implement a Bootloader&lt;/P&gt;
&lt;P&gt;You could find an application note about this topic as&amp;nbsp;&lt;STRONG&gt;Enabling Multicore Application on S32G2&amp;nbsp;&lt;/STRONG&gt;&lt;STRONG&gt;using S32G2 Platform Software Integration&lt;/STRONG&gt;, you could review it to learn how to create and configure the bootloader for your application.&lt;/P&gt;
&lt;P&gt;Also, there is a figure that shows how is the boot flow working on the device (the application note and the figure includes the implementation of the BSP, but you could only use the M7 cores if you want)&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="carlos_o_0-1749755652235.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/342749i323F9CD56A96DF55/image-size/medium?v=v2&amp;amp;px=400" role="button" title="carlos_o_0-1749755652235.png" alt="carlos_o_0-1749755652235.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 12 Jun 2025 19:17:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Core1-Not-Starting-on-S32DS399-Multi-Core-System-with-UDE-Debug/m-p/2115626#M13720</guid>
      <dc:creator>carlos_o</dc:creator>
      <dc:date>2025-06-12T19:17:20Z</dc:date>
    </item>
    <item>
      <title>回复： Core1 Not Starting on S32DS399 Multi-Core System with UDE Debug</title>
      <link>https://community.nxp.com/t5/S32G/Core1-Not-Starting-on-S32DS399-Multi-Core-System-with-UDE-Debug/m-p/2115729#M13724</link>
      <description>&lt;P&gt;hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/241501"&gt;@carlos_o&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks your responce, i have one question, please.&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Do you mean that the multi-core system can only be initialized through the bootloader, and not started via the debugger (UDE)? But debugging with UDE is still possible, right?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Regards&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Sandy&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 13 Jun 2025 00:48:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Core1-Not-Starting-on-S32DS399-Multi-Core-System-with-UDE-Debug/m-p/2115729#M13724</guid>
      <dc:creator>xlfd_1981</dc:creator>
      <dc:date>2025-06-13T00:48:04Z</dc:date>
    </item>
    <item>
      <title>回复： Core1 Not Starting on S32DS399 Multi-Core System with UDE Debug</title>
      <link>https://community.nxp.com/t5/S32G/Core1-Not-Starting-on-S32DS399-Multi-Core-System-with-UDE-Debug/m-p/2116315#M13738</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/235263"&gt;@xlfd_1981&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;NXP gives scripts to initialize a multicore debugging with Lauterbach in the GoldVIP package, in the case of the UDE you need to review with PLS to give you the corresponding script to do it.&lt;/P&gt;
&lt;P&gt;The only debugging information we have with the UDE is the following&amp;nbsp;&lt;A href="https://community.nxp.com/t5/S32-Design-Studio-Knowledge-Base/HOWTO-Install-PLS-UDE-debugger-plug-in-into-S32-Design-Studio/ta-p/1120234" target="_self"&gt;HOWTO: Install PLS UDE debugger plug-in into S32 Design Studio&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 13 Jun 2025 20:55:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Core1-Not-Starting-on-S32DS399-Multi-Core-System-with-UDE-Debug/m-p/2116315#M13738</guid>
      <dc:creator>carlos_o</dc:creator>
      <dc:date>2025-06-13T20:55:58Z</dc:date>
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