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    <title>S32GのトピックScheck - SAF SRAM ECC</title>
    <link>https://community.nxp.com/t5/S32G/Scheck-SAF-SRAM-ECC/m-p/2111071#M13646</link>
    <description>&lt;P&gt;Hi team,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I was working on Scheck SRAM test. Test target side i found there are 2 SRAM_ECC like&amp;nbsp;&lt;/P&gt;&lt;P&gt;SRAM_0_ECC and SRAM_0_ECC_LITE (LITE version provides faster execution time at cost of lower diagnostic coverage (number of test vectors is significantly reduced). i couldnt understand much about this info. so ECC test is like checking memory as per ECC logic (on Single bit error/double bit error) so less diagnostic coverage actually means??&lt;/P&gt;&lt;P&gt;if someone could drop some more information it would be helpful.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;BR,&lt;/P&gt;&lt;P&gt;Harish R&lt;/P&gt;</description>
    <pubDate>Thu, 05 Jun 2025 07:44:05 GMT</pubDate>
    <dc:creator>Harish_R</dc:creator>
    <dc:date>2025-06-05T07:44:05Z</dc:date>
    <item>
      <title>Scheck - SAF SRAM ECC</title>
      <link>https://community.nxp.com/t5/S32G/Scheck-SAF-SRAM-ECC/m-p/2111071#M13646</link>
      <description>&lt;P&gt;Hi team,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I was working on Scheck SRAM test. Test target side i found there are 2 SRAM_ECC like&amp;nbsp;&lt;/P&gt;&lt;P&gt;SRAM_0_ECC and SRAM_0_ECC_LITE (LITE version provides faster execution time at cost of lower diagnostic coverage (number of test vectors is significantly reduced). i couldnt understand much about this info. so ECC test is like checking memory as per ECC logic (on Single bit error/double bit error) so less diagnostic coverage actually means??&lt;/P&gt;&lt;P&gt;if someone could drop some more information it would be helpful.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;BR,&lt;/P&gt;&lt;P&gt;Harish R&lt;/P&gt;</description>
      <pubDate>Thu, 05 Jun 2025 07:44:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Scheck-SAF-SRAM-ECC/m-p/2111071#M13646</guid>
      <dc:creator>Harish_R</dc:creator>
      <dc:date>2025-06-05T07:44:05Z</dc:date>
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    <item>
      <title>Re: Scheck - SAF SRAM ECC</title>
      <link>https://community.nxp.com/t5/S32G/Scheck-SAF-SRAM-ECC/m-p/2112515#M13660</link>
      <description>&lt;P&gt;Hello,&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/242921"&gt;@Harish_R&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks fo your post and sorry for late response.&lt;/P&gt;
&lt;P&gt;From my understanding, the&amp;nbsp;&lt;SPAN&gt;less diagnostic coverage here may mean that some errors may go unnoticed, and/or some of the noticed fault may not be corrected/handled, which is caused by the&amp;nbsp;&lt;SPAN class="fontstyle0"&gt;number of test vectors is significantly reduced.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Chenyin&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 09 Jun 2025 04:24:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Scheck-SAF-SRAM-ECC/m-p/2112515#M13660</guid>
      <dc:creator>chenyin_h</dc:creator>
      <dc:date>2025-06-09T04:24:50Z</dc:date>
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