topic Re: S32G Clock in S32G

S32G Clock

liujian_abup — Tue, 13 May 2025 06:50:32 GMT

hi, nxp:

Currently, there is a problem. The M7 core code is placed in the SD card and started in u-boot. However, the clock and interrupt table are configured in the M7 code, which conflicts with A53; If the M7 starts first, the A53 cannot start normally.

There is currently a solution idea:

Interrupt table conflict handling solution: The peripheral devices used by M7 and A53 are all uncontrollable and are all disenabled in the device tree.

2. Clock conflict solution: Check the current system configuration clock of A53. If the M7 module is configured to be the same, can this solve the conflict?

Problem point:

How can A53 query all clock configuration information

Are the above two schemes feasible?

Thank you!

Re: S32G Clock

Joey_z — Tue, 13 May 2025 10:39:59 GMT

hi,liujian_abup

Thank you for contacting us.

In general, for multi-core boot mode, using bootloader to boot M and A core is a more formal way, but may be will have some multi-core conflicts, such as peripheral configuration and clock conflicts. For the conflict between peripherals and clocks, the arm-trusted-firmware/fdts/s32cc.dtsi and s32gxxxa-rdb.dtsi files in ATF need to be modified, consistent with the M core. Regarding your startup method, I think you can also use this way to resolve conflicts.

Hope it can help you.

Joey

Re: S32G Clock

liujian_abup — Wed, 14 May 2025 05:33:00 GMT

hello, Joey_z

Which registers' values should be modified in the ATF device tree? I modified fxosc, firc, sirc, ftm0_ext, ftm1_ext, gmac0_ext_rx, gmac0_ext_tx, gmac0_rmii_ref, and gmac0_ext_ts; The MPU still fails to start normally.

In the current CAN example project of the MCU clock configuration, I configured the device tree according to it.

Thank you!

Re: S32G Clock

Joey_z — Wed, 14 May 2025 06:38:12 GMT

hi,liujian_abup

Which CAN example project are you using?

Joey

Re: S32G Clock

liujian_abup — Wed, 14 May 2025 07:02:24 GMT

hi， Joey_z：

Re: S32G Clock

Joey_z — Wed, 14 May 2025 13:15:59 GMT

hi，liujian_abup

I think you can try not to initial the clock in M core.

If you can setup successfully, then, Initial the flexcan_can clock to 80Mhz in A core.

This is my link file and the way of setup M core in uboot.

I suggest that if CAN be successfully used, you can start from the M core and gradually troubleshoot clock conflicts.

Hope it can help you.

Joey

Re: S32G Clock

liujian_abup — Thu, 15 May 2025 02:55:44 GMT

hi, Joey_z

Using this method, both my M7 and A53 could start up normally. However, after such processing, the baud rate of the CAN driver was abnormal (by default, it was configured as 500kb for 80M).

The two core clocks of the S32G399A chip should not be shared but only conflict. It seems that the clock synchronization needs to be configured to be the same, right?

The above is my understanding.

Thank you for your support!

Re: S32G Clock

Joey_z — Thu, 15 May 2025 06:33:05 GMT

hi,liujian_abup

Clock conflicts can cause boot or peripheral issues.

The clock used in the M core should be synchronized as much as possible in the A core or not configured at all.

Joey

Re: S32G Clock

liujian_abup — Thu, 15 May 2025 06:44:35 GMT

hi, Joey_z

Yes;

If the clock is not set, the CAN tool of the M7 core malfunctions, and the baud rate register value cannot be recognized. This idea was killed

2. When setting the clock, the M7 core worked properly, but the A53 couldn't start. During previous communication, I also tried to modify the device tree module in the ATF to align some system input clocks, but the A53 still couldn't start normally.

What we need your support for now is the second point. Only in this way can it start up normally.

Thank you!

Re: S32G Clock

Joey_z — Mon, 19 May 2025 08:07:38 GMT

hi,liujian_abup

Thank you for your reply and information.

I'm trying to test this issue for you and will reply to you as soon as there is a result.

Joey

Re: S32G Clock

Joey_z — Tue, 20 May 2025 10:29:28 GMT

hi，liujian_abup

Sorry for replying late.

Based on discussing your issue with internal experts. Block Clock_Ip_Init(&Mcu_aClockConfigPB[0]); It should be a relatively easy method to implement.

About your baud rate issue, it should work and perhaps no issue for the demo purpose. It might be caused by the occurrence of error frames. Please check your configuration of demo in M core.

I tested the demo by cancel the Clock_Ip_Init(&Mcu_aClockConfigPB[0]);

This is A core Flexcan1 to receive frame from Flexcan0 in M core. The external line need connection.

Please note that The baud rate I'm using is 250k and I added A delay to the M core and ran the M core code only after the A core Kernel was fully completed.

Hope it can help you.

Joey