<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>S32Gのトピックdwmac eth0 failed to enable PTP reference clock: -EIO with SDK BSP43 release on RDB3</title>
    <link>https://community.nxp.com/t5/S32G/dwmac-eth0-failed-to-enable-PTP-reference-clock-EIO-with-SDK/m-p/2061784#M12941</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I tested SDK BSP43 release on RDB3 board, and I found that, the ptp reference clock enabled failed with the following message:&lt;/P&gt;&lt;P class="lia-indent-padding-left-30px"&gt;root@s32g399ardb3:~# dmesg | grep dwmac&lt;BR /&gt;[ 4.850647] s32cc-dwmac 4033c000.ethernet: IRQ eth_wake_irq not found&lt;BR /&gt;[ 4.857202] s32cc-dwmac 4033c000.ethernet: IRQ eth_lpi not found&lt;BR /&gt;[ 4.863640] s32cc-dwmac 4033c000.ethernet: User ID: 0x10, Synopsys ID: 0x52&lt;BR /&gt;[ 4.870727] s32cc-dwmac 4033c000.ethernet: DWMAC4/5&lt;BR /&gt;[ 4.875779] s32cc-dwmac 4033c000.ethernet: DMA HW capability register supported&lt;BR /&gt;[ 4.883209] s32cc-dwmac 4033c000.ethernet: RX Checksum Offload Engine supported&lt;BR /&gt;[ 4.890637] s32cc-dwmac 4033c000.ethernet: TX Checksum insertion supported&lt;BR /&gt;[ 4.897623] s32cc-dwmac 4033c000.ethernet: Wake-Up On Lan supported&lt;BR /&gt;[ 4.904030] s32cc-dwmac 4033c000.ethernet: Enable RX Mitigation via HW Watchdog Timer&lt;BR /&gt;[ 4.911992] s32cc-dwmac 4033c000.ethernet: Enabled L3L4 Flow TC (entries=8)&lt;BR /&gt;[ 4.919068] s32cc-dwmac 4033c000.ethernet: Enabled RFS Flow TC (entries=10)&lt;BR /&gt;[ 4.926150] s32cc-dwmac 4033c000.ethernet: Enabling HW TC (entries=256, max_off=256)&lt;BR /&gt;[ 4.934023] s32cc-dwmac 4033c000.ethernet: Using 32/32 bits DMA host/device width&lt;BR /&gt;[ 9.792490] s32cc-dwmac 4033c000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-0&lt;BR /&gt;[ 9.792794] s32cc-dwmac 4033c000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-1&lt;BR /&gt;[ 9.793051] s32cc-dwmac 4033c000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-2&lt;BR /&gt;[ 9.793314] s32cc-dwmac 4033c000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-3&lt;BR /&gt;[ 9.793585] s32cc-dwmac 4033c000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-4&lt;BR /&gt;[ 9.861296] s32cc-dwmac 4033c000.ethernet eth0: PHY [stmmac-0:01] driver [Micrel KSZ9031 Gigabit PHY] (irq=POLL)&lt;BR /&gt;[ 9.870824] dwmac4: Master AXI performs any burst length&lt;BR /&gt;[ 9.870966] s32cc-dwmac 4033c000.ethernet eth0: Enabling Safety Features&lt;BR /&gt;&lt;STRONG&gt;[ 9.871048] s32cc-dwmac 4033c000.ethernet eth0: failed to enable PTP reference clock: -EIO&lt;/STRONG&gt;&lt;BR /&gt;[ 10.076859] s32cc-dwmac 4033c000.ethernet eth0: IEEE 1588-2008 Advanced Timestamp supported&lt;BR /&gt;[ 10.077137] s32cc-dwmac 4033c000.ethernet eth0: registered PTP clock&lt;BR /&gt;[ 10.077554] s32cc-dwmac 4033c000.ethernet eth0: FPE workqueue start&lt;BR /&gt;[ 10.077567] s32cc-dwmac 4033c000.ethernet eth0: configuring for phy/rgmii-id link mode&lt;BR /&gt;root@s32g399ardb3:~# uname -a&lt;BR /&gt;Linux s32g399ardb3 6.6.52-rt43-g1a29a32be610 #1 SMP PREEMPT Thu Nov 21 09:35:09 UTC 2024 aarch64 aarch64 aarch64 GNU/Linux&lt;BR /&gt;&lt;A href="mailto:root@s32g399ardb3:~" target="_blank"&gt;root@s32g399ardb3:~#&lt;/A&gt;&lt;/P&gt;&lt;P class="lia-indent-padding-left-30px"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;But if the pfe enabled, the failure message will disappear. I checked source codes, but it seems relate with atf codes, not the kernel codes.&lt;/P&gt;&lt;P&gt;Would you please help to check this issue?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Zhantao&lt;/P&gt;</description>
    <pubDate>Fri, 14 Mar 2025 05:29:28 GMT</pubDate>
    <dc:creator>hittzt</dc:creator>
    <dc:date>2025-03-14T05:29:28Z</dc:date>
    <item>
      <title>dwmac eth0 failed to enable PTP reference clock: -EIO with SDK BSP43 release on RDB3</title>
      <link>https://community.nxp.com/t5/S32G/dwmac-eth0-failed-to-enable-PTP-reference-clock-EIO-with-SDK/m-p/2061784#M12941</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I tested SDK BSP43 release on RDB3 board, and I found that, the ptp reference clock enabled failed with the following message:&lt;/P&gt;&lt;P class="lia-indent-padding-left-30px"&gt;root@s32g399ardb3:~# dmesg | grep dwmac&lt;BR /&gt;[ 4.850647] s32cc-dwmac 4033c000.ethernet: IRQ eth_wake_irq not found&lt;BR /&gt;[ 4.857202] s32cc-dwmac 4033c000.ethernet: IRQ eth_lpi not found&lt;BR /&gt;[ 4.863640] s32cc-dwmac 4033c000.ethernet: User ID: 0x10, Synopsys ID: 0x52&lt;BR /&gt;[ 4.870727] s32cc-dwmac 4033c000.ethernet: DWMAC4/5&lt;BR /&gt;[ 4.875779] s32cc-dwmac 4033c000.ethernet: DMA HW capability register supported&lt;BR /&gt;[ 4.883209] s32cc-dwmac 4033c000.ethernet: RX Checksum Offload Engine supported&lt;BR /&gt;[ 4.890637] s32cc-dwmac 4033c000.ethernet: TX Checksum insertion supported&lt;BR /&gt;[ 4.897623] s32cc-dwmac 4033c000.ethernet: Wake-Up On Lan supported&lt;BR /&gt;[ 4.904030] s32cc-dwmac 4033c000.ethernet: Enable RX Mitigation via HW Watchdog Timer&lt;BR /&gt;[ 4.911992] s32cc-dwmac 4033c000.ethernet: Enabled L3L4 Flow TC (entries=8)&lt;BR /&gt;[ 4.919068] s32cc-dwmac 4033c000.ethernet: Enabled RFS Flow TC (entries=10)&lt;BR /&gt;[ 4.926150] s32cc-dwmac 4033c000.ethernet: Enabling HW TC (entries=256, max_off=256)&lt;BR /&gt;[ 4.934023] s32cc-dwmac 4033c000.ethernet: Using 32/32 bits DMA host/device width&lt;BR /&gt;[ 9.792490] s32cc-dwmac 4033c000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-0&lt;BR /&gt;[ 9.792794] s32cc-dwmac 4033c000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-1&lt;BR /&gt;[ 9.793051] s32cc-dwmac 4033c000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-2&lt;BR /&gt;[ 9.793314] s32cc-dwmac 4033c000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-3&lt;BR /&gt;[ 9.793585] s32cc-dwmac 4033c000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-4&lt;BR /&gt;[ 9.861296] s32cc-dwmac 4033c000.ethernet eth0: PHY [stmmac-0:01] driver [Micrel KSZ9031 Gigabit PHY] (irq=POLL)&lt;BR /&gt;[ 9.870824] dwmac4: Master AXI performs any burst length&lt;BR /&gt;[ 9.870966] s32cc-dwmac 4033c000.ethernet eth0: Enabling Safety Features&lt;BR /&gt;&lt;STRONG&gt;[ 9.871048] s32cc-dwmac 4033c000.ethernet eth0: failed to enable PTP reference clock: -EIO&lt;/STRONG&gt;&lt;BR /&gt;[ 10.076859] s32cc-dwmac 4033c000.ethernet eth0: IEEE 1588-2008 Advanced Timestamp supported&lt;BR /&gt;[ 10.077137] s32cc-dwmac 4033c000.ethernet eth0: registered PTP clock&lt;BR /&gt;[ 10.077554] s32cc-dwmac 4033c000.ethernet eth0: FPE workqueue start&lt;BR /&gt;[ 10.077567] s32cc-dwmac 4033c000.ethernet eth0: configuring for phy/rgmii-id link mode&lt;BR /&gt;root@s32g399ardb3:~# uname -a&lt;BR /&gt;Linux s32g399ardb3 6.6.52-rt43-g1a29a32be610 #1 SMP PREEMPT Thu Nov 21 09:35:09 UTC 2024 aarch64 aarch64 aarch64 GNU/Linux&lt;BR /&gt;&lt;A href="mailto:root@s32g399ardb3:~" target="_blank"&gt;root@s32g399ardb3:~#&lt;/A&gt;&lt;/P&gt;&lt;P class="lia-indent-padding-left-30px"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;But if the pfe enabled, the failure message will disappear. I checked source codes, but it seems relate with atf codes, not the kernel codes.&lt;/P&gt;&lt;P&gt;Would you please help to check this issue?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Zhantao&lt;/P&gt;</description>
      <pubDate>Fri, 14 Mar 2025 05:29:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/dwmac-eth0-failed-to-enable-PTP-reference-clock-EIO-with-SDK/m-p/2061784#M12941</guid>
      <dc:creator>hittzt</dc:creator>
      <dc:date>2025-03-14T05:29:28Z</dc:date>
    </item>
    <item>
      <title>Re: dwmac eth0 failed to enable PTP reference clock: -EIO with SDK BSP43 release on RDB3</title>
      <link>https://community.nxp.com/t5/S32G/dwmac-eth0-failed-to-enable-PTP-reference-clock-EIO-with-SDK/m-p/2063412#M12974</link>
      <description>&lt;P&gt;Hello,&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/135277"&gt;@hittzt&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks for the post.&lt;/P&gt;
&lt;P&gt;From my opinion, the GMAC PTP clock may use the corresponding clock of PFE, which caused such prints:&lt;/P&gt;
&lt;DIV id="tinyMceEditor_48aaa2b4f3652fchenyin_h_0" class="mceNonEditable lia-copypaste-placeholder"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="chenyin_h_1-1742271616111.jpeg" style="width: 800px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/328533i583803EF4A65CD87/image-size/medium?v=v2&amp;amp;px=400" role="button" title="chenyin_h_1-1742271616111.jpeg" alt="chenyin_h_1-1742271616111.jpeg" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Chenyin&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 18 Mar 2025 04:22:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/dwmac-eth0-failed-to-enable-PTP-reference-clock-EIO-with-SDK/m-p/2063412#M12974</guid>
      <dc:creator>chenyin_h</dc:creator>
      <dc:date>2025-03-18T04:22:00Z</dc:date>
    </item>
    <item>
      <title>Re: dwmac eth0 failed to enable PTP reference clock: -EIO with SDK BSP43 release on RDB3</title>
      <link>https://community.nxp.com/t5/S32G/dwmac-eth0-failed-to-enable-PTP-reference-clock-EIO-with-SDK/m-p/2065276#M13024</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/24163"&gt;@chenyin_h&lt;/a&gt;,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks for your reply.&lt;/P&gt;&lt;P&gt;I know the point you said, but it seems not the reason of the issue.&lt;/P&gt;&lt;P&gt;Your image is the hardware relationship, not the codes's.&lt;/P&gt;&lt;P&gt;And the root cause seems in the following commits of arm-trusted-firmware codes:&lt;/P&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;STRONG&gt;From a43c123995a95de12f5cd1e5eacb6af9f6a84993 Mon Sep 17 00:00:00 2001&lt;/STRONG&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;STRONG&gt;From: Andrei Botila &amp;lt;andrei.botila@nxp.com&amp;gt;&lt;/STRONG&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;STRONG&gt;Date: Mon, 22 Jul 2024 10:24:24 +0300&lt;/STRONG&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;STRONG&gt;Subject: [PATCH 83/98] s32cc: clocks: add GMAC MII support&lt;/STRONG&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;STRONG&gt;Enable Tx clock for GMAC MII mode. Also set the necessary&lt;/STRONG&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;STRONG&gt;Tx and Rx clock for it.&lt;/STRONG&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;STRONG&gt;Issue: ALB-10056&lt;/STRONG&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;STRONG&gt;Signed-off-by: Andrei Botila &amp;lt;andrei.botila@nxp.com&amp;gt;&lt;/STRONG&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;and&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;STRONG&gt;From 718663a00e7691f0959a748a75c0e4c665703c19 Mon Sep 17 00:00:00 2001&lt;/STRONG&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;STRONG&gt;From: Andrei Botila &amp;lt;andrei.botila@nxp.com&amp;gt;&lt;/STRONG&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;STRONG&gt;Date: Mon, 22 Jul 2024 10:24:37 +0300&lt;/STRONG&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;STRONG&gt;Subject: [PATCH 84/98] s32cc: clocks: add GMAC RMII support&lt;/STRONG&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;STRONG&gt;Enable GMAC RMII mode. Also set the necessary Tx and Rx&lt;/STRONG&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;STRONG&gt;clock for it.&lt;/STRONG&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;STRONG&gt;Issue: ALB-10056&lt;/STRONG&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;STRONG&gt;Signed-off-by: Andrei Botila &amp;lt;andrei.botila@nxp.com&amp;gt;&lt;/STRONG&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;If revert these two commits, then the issue will be disappeare.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;So would you please help to check it again and give a fix or workaroud?&lt;/DIV&gt;&lt;DIV&gt;And I will keep working to find a way to fix it too.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Thanks,&lt;/DIV&gt;&lt;DIV&gt;Zhantao&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Thu, 20 Mar 2025 06:19:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/dwmac-eth0-failed-to-enable-PTP-reference-clock-EIO-with-SDK/m-p/2065276#M13024</guid>
      <dc:creator>hittzt</dc:creator>
      <dc:date>2025-03-20T06:19:05Z</dc:date>
    </item>
    <item>
      <title>Re: dwmac eth0 failed to enable PTP reference clock: -EIO with SDK BSP43 release on RDB3</title>
      <link>https://community.nxp.com/t5/S32G/dwmac-eth0-failed-to-enable-PTP-reference-clock-EIO-with-SDK/m-p/2066835#M13045</link>
      <description>&lt;P&gt;Hello,&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/135277"&gt;@hittzt&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks for your detailed description on the issue, sure, I will also check on it.&lt;/P&gt;
&lt;P&gt;May I know if there are any actual impact on your project? maybe you need to use the 1588 of GMAC0 without PFE enabled?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Chenyin&lt;/P&gt;</description>
      <pubDate>Mon, 24 Mar 2025 03:09:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/dwmac-eth0-failed-to-enable-PTP-reference-clock-EIO-with-SDK/m-p/2066835#M13045</guid>
      <dc:creator>chenyin_h</dc:creator>
      <dc:date>2025-03-24T03:09:20Z</dc:date>
    </item>
    <item>
      <title>Re: dwmac eth0 failed to enable PTP reference clock: -EIO with SDK BSP43 release on RDB3</title>
      <link>https://community.nxp.com/t5/S32G/dwmac-eth0-failed-to-enable-PTP-reference-clock-EIO-with-SDK/m-p/2066967#M13048</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/24163"&gt;@chenyin_h&lt;/a&gt;,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Oh, yes, the pfe is a optional feature currently, I may use only gmac0's 1588 of the board without the pfe feature.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Zhantao&lt;/P&gt;</description>
      <pubDate>Mon, 24 Mar 2025 06:45:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/dwmac-eth0-failed-to-enable-PTP-reference-clock-EIO-with-SDK/m-p/2066967#M13048</guid>
      <dc:creator>hittzt</dc:creator>
      <dc:date>2025-03-24T06:45:11Z</dc:date>
    </item>
    <item>
      <title>Re: dwmac eth0 failed to enable PTP reference clock: -EIO with SDK BSP43 release on RDB3</title>
      <link>https://community.nxp.com/t5/S32G/dwmac-eth0-failed-to-enable-PTP-reference-clock-EIO-with-SDK/m-p/2077937#M13197</link>
      <description>&lt;P&gt;Hello,&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/135277"&gt;@hittzt&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks for your patience.&lt;/P&gt;
&lt;P&gt;With further checking with internal teams, it is confirmed to be a bug and is planned to be fixed in the following BSPs.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Chenyin&lt;/P&gt;</description>
      <pubDate>Thu, 10 Apr 2025 04:22:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/dwmac-eth0-failed-to-enable-PTP-reference-clock-EIO-with-SDK/m-p/2077937#M13197</guid>
      <dc:creator>chenyin_h</dc:creator>
      <dc:date>2025-04-10T04:22:28Z</dc:date>
    </item>
  </channel>
</rss>

