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    <title>topic Re: Difference between S32G DMA and Noc in S32G</title>
    <link>https://community.nxp.com/t5/S32G/Difference-between-S32G-DMA-and-Noc/m-p/2055874#M12836</link>
    <description>&lt;P&gt;Hello,&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/247551"&gt;@Hi-Rain&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks for your post.&lt;/P&gt;
&lt;ARTICLE data-content="[{&amp;quot;type&amp;quot;:&amp;quot;block&amp;quot;,&amp;quot;id&amp;quot;:&amp;quot;vY6y-1741140780973&amp;quot;,&amp;quot;name&amp;quot;:&amp;quot;paragraph&amp;quot;,&amp;quot;data&amp;quot;:{&amp;quot;version&amp;quot;:1},&amp;quot;nodes&amp;quot;:[{&amp;quot;type&amp;quot;:&amp;quot;text&amp;quot;,&amp;quot;id&amp;quot;:&amp;quot;g33x-1741140780971&amp;quot;,&amp;quot;leaves&amp;quot;:[{&amp;quot;text&amp;quot;:&amp;quot;NoC&amp;nbsp;is&amp;nbsp;an&amp;nbsp;interconnect&amp;nbsp;matrix&amp;nbsp;that&amp;nbsp;supports&amp;nbsp;communication&amp;nbsp;between&amp;nbsp;various&amp;nbsp;initiators&amp;nbsp;and&amp;nbsp;targets,&amp;nbsp;including&amp;nbsp;clusters/cores/peripherals/sram,&amp;nbsp;as&amp;nbsp;introduced&amp;nbsp;from&amp;nbsp;the&amp;nbsp;RM,&amp;nbsp;it&amp;nbsp;supports&amp;nbsp;various&amp;nbsp;industry&amp;nbsp;standard&amp;nbsp;socket&amp;nbsp;protocols&amp;nbsp;like&amp;nbsp;AXI,&amp;nbsp;AHB,&amp;nbsp;so&amp;nbsp;it&amp;nbsp;is&amp;nbsp;designed&amp;nbsp;to&amp;nbsp;carry&amp;nbsp;the&amp;nbsp;protocols&amp;nbsp;that&amp;nbsp;connect&amp;nbsp;each&amp;nbsp;of&amp;nbsp;part&amp;nbsp;on&amp;nbsp;SOC.&amp;quot;,&amp;quot;marks&amp;quot;:[]}]}],&amp;quot;state&amp;quot;:{}},{&amp;quot;type&amp;quot;:&amp;quot;block&amp;quot;,&amp;quot;id&amp;quot;:&amp;quot;bDVe-1741141256171&amp;quot;,&amp;quot;name&amp;quot;:&amp;quot;paragraph&amp;quot;,&amp;quot;data&amp;quot;:{&amp;quot;version&amp;quot;:1},&amp;quot;nodes&amp;quot;:[{&amp;quot;type&amp;quot;:&amp;quot;text&amp;quot;,&amp;quot;id&amp;quot;:&amp;quot;g5KD-1741141256169&amp;quot;,&amp;quot;leaves&amp;quot;:[{&amp;quot;text&amp;quot;:&amp;quot;DMA's&amp;nbsp;&amp;quot;,&amp;quot;marks&amp;quot;:[]},{&amp;quot;text&amp;quot;:&amp;quot;main&amp;nbsp;purpose&amp;nbsp;is&amp;nbsp;to&amp;nbsp;enable&amp;nbsp;peripheral&amp;nbsp;devices&amp;nbsp;to&amp;nbsp;directly&amp;nbsp;access&amp;nbsp;the&amp;nbsp;system&amp;nbsp;memory&amp;nbsp;without&amp;nbsp;the&amp;nbsp;need&amp;nbsp;for&amp;nbsp;continuous&amp;nbsp;intervention&amp;nbsp;from&amp;nbsp;the&amp;nbsp;CPU,&amp;nbsp;thus&amp;nbsp;improving&amp;nbsp;the&amp;nbsp;overall&amp;nbsp;efficiency&amp;nbsp;and&amp;nbsp;performance&amp;nbsp;of&amp;nbsp;the&amp;nbsp;system.&amp;nbsp;it&amp;nbsp;is&amp;nbsp;usually&amp;nbsp;used&amp;nbsp;for&amp;nbsp;moving&amp;nbsp;large&amp;nbsp;chunck&amp;nbsp;of&amp;nbsp;data&amp;nbsp;from&amp;nbsp;memory&amp;nbsp;to&amp;nbsp;memory(like&amp;nbsp;DDR,&amp;nbsp;SRAM,&amp;nbsp;PCIe).&amp;quot;,&amp;quot;marks&amp;quot;:[{&amp;quot;type&amp;quot;:&amp;quot;color&amp;quot;,&amp;quot;value&amp;quot;:&amp;quot;#000000&amp;quot;},{&amp;quot;type&amp;quot;:&amp;quot;backgroundColor&amp;quot;,&amp;quot;value&amp;quot;:&amp;quot;rgb(255,&amp;nbsp;255,&amp;nbsp;255)&amp;quot;},{&amp;quot;type&amp;quot;:&amp;quot;fontFamily&amp;quot;,&amp;quot;value&amp;quot;:&amp;quot;Arial&amp;quot;}]}]}],&amp;quot;state&amp;quot;:{}}]"&gt;
&lt;DIV&gt;From my understanding, NoC is an interconnect matrix that supports communication between various initiators and targets, including cores/peripherals/SRAM, it supports various industry standard socket protocols like AXI, AHB, so it is mainly used to carry the protocols that connect each of part on SOC, which is mainly used for the communication on SOC.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;DMA's &lt;SPAN&gt;main purpose is to enable peripheral devices to directly access the system memory without the need for continuous intervention from the CPU, thus improving the overall efficiency and performance of the system. it is usually used for moving large chunk of data from memory to memory(like DDR, SRAM, PCIe).&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;BR&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;Chenyin&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;/ARTICLE&gt;</description>
    <pubDate>Wed, 05 Mar 2025 02:30:39 GMT</pubDate>
    <dc:creator>chenyin_h</dc:creator>
    <dc:date>2025-03-05T02:30:39Z</dc:date>
    <item>
      <title>Difference between S32G DMA and Noc</title>
      <link>https://community.nxp.com/t5/S32G/Difference-between-S32G-DMA-and-Noc/m-p/2055107#M12810</link>
      <description>&lt;P&gt;Hi deer NXP expert：&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; When I read S32G3 Reference Manual，I have a question on&amp;nbsp;difference between S32G DMA and Noc. Since NoC support communication between cores, peripherals and SRAM, and DMA also transfer data between memory block and I/O block(without core? Im not sure).&lt;/P&gt;</description>
      <pubDate>Tue, 04 Mar 2025 02:03:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Difference-between-S32G-DMA-and-Noc/m-p/2055107#M12810</guid>
      <dc:creator>Hi-Rain</dc:creator>
      <dc:date>2025-03-04T02:03:53Z</dc:date>
    </item>
    <item>
      <title>Re: Difference between S32G DMA and Noc</title>
      <link>https://community.nxp.com/t5/S32G/Difference-between-S32G-DMA-and-Noc/m-p/2055874#M12836</link>
      <description>&lt;P&gt;Hello,&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/247551"&gt;@Hi-Rain&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks for your post.&lt;/P&gt;
&lt;ARTICLE data-content="[{&amp;quot;type&amp;quot;:&amp;quot;block&amp;quot;,&amp;quot;id&amp;quot;:&amp;quot;vY6y-1741140780973&amp;quot;,&amp;quot;name&amp;quot;:&amp;quot;paragraph&amp;quot;,&amp;quot;data&amp;quot;:{&amp;quot;version&amp;quot;:1},&amp;quot;nodes&amp;quot;:[{&amp;quot;type&amp;quot;:&amp;quot;text&amp;quot;,&amp;quot;id&amp;quot;:&amp;quot;g33x-1741140780971&amp;quot;,&amp;quot;leaves&amp;quot;:[{&amp;quot;text&amp;quot;:&amp;quot;NoC&amp;nbsp;is&amp;nbsp;an&amp;nbsp;interconnect&amp;nbsp;matrix&amp;nbsp;that&amp;nbsp;supports&amp;nbsp;communication&amp;nbsp;between&amp;nbsp;various&amp;nbsp;initiators&amp;nbsp;and&amp;nbsp;targets,&amp;nbsp;including&amp;nbsp;clusters/cores/peripherals/sram,&amp;nbsp;as&amp;nbsp;introduced&amp;nbsp;from&amp;nbsp;the&amp;nbsp;RM,&amp;nbsp;it&amp;nbsp;supports&amp;nbsp;various&amp;nbsp;industry&amp;nbsp;standard&amp;nbsp;socket&amp;nbsp;protocols&amp;nbsp;like&amp;nbsp;AXI,&amp;nbsp;AHB,&amp;nbsp;so&amp;nbsp;it&amp;nbsp;is&amp;nbsp;designed&amp;nbsp;to&amp;nbsp;carry&amp;nbsp;the&amp;nbsp;protocols&amp;nbsp;that&amp;nbsp;connect&amp;nbsp;each&amp;nbsp;of&amp;nbsp;part&amp;nbsp;on&amp;nbsp;SOC.&amp;quot;,&amp;quot;marks&amp;quot;:[]}]}],&amp;quot;state&amp;quot;:{}},{&amp;quot;type&amp;quot;:&amp;quot;block&amp;quot;,&amp;quot;id&amp;quot;:&amp;quot;bDVe-1741141256171&amp;quot;,&amp;quot;name&amp;quot;:&amp;quot;paragraph&amp;quot;,&amp;quot;data&amp;quot;:{&amp;quot;version&amp;quot;:1},&amp;quot;nodes&amp;quot;:[{&amp;quot;type&amp;quot;:&amp;quot;text&amp;quot;,&amp;quot;id&amp;quot;:&amp;quot;g5KD-1741141256169&amp;quot;,&amp;quot;leaves&amp;quot;:[{&amp;quot;text&amp;quot;:&amp;quot;DMA's&amp;nbsp;&amp;quot;,&amp;quot;marks&amp;quot;:[]},{&amp;quot;text&amp;quot;:&amp;quot;main&amp;nbsp;purpose&amp;nbsp;is&amp;nbsp;to&amp;nbsp;enable&amp;nbsp;peripheral&amp;nbsp;devices&amp;nbsp;to&amp;nbsp;directly&amp;nbsp;access&amp;nbsp;the&amp;nbsp;system&amp;nbsp;memory&amp;nbsp;without&amp;nbsp;the&amp;nbsp;need&amp;nbsp;for&amp;nbsp;continuous&amp;nbsp;intervention&amp;nbsp;from&amp;nbsp;the&amp;nbsp;CPU,&amp;nbsp;thus&amp;nbsp;improving&amp;nbsp;the&amp;nbsp;overall&amp;nbsp;efficiency&amp;nbsp;and&amp;nbsp;performance&amp;nbsp;of&amp;nbsp;the&amp;nbsp;system.&amp;nbsp;it&amp;nbsp;is&amp;nbsp;usually&amp;nbsp;used&amp;nbsp;for&amp;nbsp;moving&amp;nbsp;large&amp;nbsp;chunck&amp;nbsp;of&amp;nbsp;data&amp;nbsp;from&amp;nbsp;memory&amp;nbsp;to&amp;nbsp;memory(like&amp;nbsp;DDR,&amp;nbsp;SRAM,&amp;nbsp;PCIe).&amp;quot;,&amp;quot;marks&amp;quot;:[{&amp;quot;type&amp;quot;:&amp;quot;color&amp;quot;,&amp;quot;value&amp;quot;:&amp;quot;#000000&amp;quot;},{&amp;quot;type&amp;quot;:&amp;quot;backgroundColor&amp;quot;,&amp;quot;value&amp;quot;:&amp;quot;rgb(255,&amp;nbsp;255,&amp;nbsp;255)&amp;quot;},{&amp;quot;type&amp;quot;:&amp;quot;fontFamily&amp;quot;,&amp;quot;value&amp;quot;:&amp;quot;Arial&amp;quot;}]}]}],&amp;quot;state&amp;quot;:{}}]"&gt;
&lt;DIV&gt;From my understanding, NoC is an interconnect matrix that supports communication between various initiators and targets, including cores/peripherals/SRAM, it supports various industry standard socket protocols like AXI, AHB, so it is mainly used to carry the protocols that connect each of part on SOC, which is mainly used for the communication on SOC.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;DMA's &lt;SPAN&gt;main purpose is to enable peripheral devices to directly access the system memory without the need for continuous intervention from the CPU, thus improving the overall efficiency and performance of the system. it is usually used for moving large chunk of data from memory to memory(like DDR, SRAM, PCIe).&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;BR&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;Chenyin&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;/ARTICLE&gt;</description>
      <pubDate>Wed, 05 Mar 2025 02:30:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Difference-between-S32G-DMA-and-Noc/m-p/2055874#M12836</guid>
      <dc:creator>chenyin_h</dc:creator>
      <dc:date>2025-03-05T02:30:39Z</dc:date>
    </item>
    <item>
      <title>Re: Difference between S32G DMA and Noc</title>
      <link>https://community.nxp.com/t5/S32G/Difference-between-S32G-DMA-and-Noc/m-p/2056036#M12839</link>
      <description>&lt;P&gt;Thanks a lot.&amp;nbsp;@&lt;A href="https://community.nxp.com/t5/user/viewprofilepage/user-id/24163" target="_self"&gt;&lt;SPAN class=""&gt;chenyin_h&lt;/SPAN&gt;&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Your response has thoroughly addressed my concerns!&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;And I have another question.&lt;/P&gt;&lt;P&gt;As we can see in S32G safety manual that there are several safety mechanism to protect NoC from failure such as&amp;nbsp;SM1.NOC.PKT_PROT，SM1.NOC.RESILIENCE. If I use E2E to protect the&amp;nbsp; communication ,&amp;nbsp; do I still need to implement these safety mechanisms?&lt;/P&gt;</description>
      <pubDate>Wed, 05 Mar 2025 07:04:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Difference-between-S32G-DMA-and-Noc/m-p/2056036#M12839</guid>
      <dc:creator>Hi-Rain</dc:creator>
      <dc:date>2025-03-05T07:04:08Z</dc:date>
    </item>
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