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    <title>topic Re: S32G274 SPI clock phase configuration in S32G</title>
    <link>https://community.nxp.com/t5/S32G/S32G274-SPI-clock-phase-configuration/m-p/2027191#M12319</link>
    <description>&lt;P&gt;Hello,&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/218312"&gt;@Apopo&lt;/a&gt;&amp;nbsp;&lt;BR /&gt;Thanks for your post.&lt;/P&gt;
&lt;P&gt;From my understanding, the settings you have made is actually&amp;nbsp;&lt;SPAN&gt;CPOL=0, CPHA=1.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;If you want to set with&amp;nbsp;CPOL=0, CPHA=0, then the following settings for your reference.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="chenyin_h_0-1736822615793.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/319396iAEB071FE8265B586/image-size/medium?v=v2&amp;amp;px=400" role="button" title="chenyin_h_0-1736822615793.png" alt="chenyin_h_0-1736822615793.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;I hope it will help.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Chenyin&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Tue, 14 Jan 2025 02:45:10 GMT</pubDate>
    <dc:creator>chenyin_h</dc:creator>
    <dc:date>2025-01-14T02:45:10Z</dc:date>
    <item>
      <title>S32G274 SPI clock phase configuration</title>
      <link>https://community.nxp.com/t5/S32G/S32G274-SPI-clock-phase-configuration/m-p/2026637#M12302</link>
      <description>&lt;P&gt;&lt;SPAN&gt;Use S32DS3.5 and select Example core &lt;/SPAN&gt;à&lt;SPAN&gt; Lpspi_Ip_Transter_S32G274A_M7&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="image.png" style="width: 353px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/319222i752D8484ABEE9FFF/image-size/large?v=v2&amp;amp;px=999" role="button" title="image.png" alt="image.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;The configuration needs to be set to CPOL=0, CPHA=0. Is the following setting correct?&lt;/SPAN&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="image.png" style="width: 303px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/319225i4F136FDC496311E6/image-size/large?v=v2&amp;amp;px=999" role="button" title="image.png" alt="image.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;If I want to set CPOL=0, CPHA=1, how do I set it?&lt;/P&gt;</description>
      <pubDate>Mon, 13 Jan 2025 09:49:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G274-SPI-clock-phase-configuration/m-p/2026637#M12302</guid>
      <dc:creator>Apopo</dc:creator>
      <dc:date>2025-01-13T09:49:42Z</dc:date>
    </item>
    <item>
      <title>Re: S32G274 SPI clock phase configuration</title>
      <link>https://community.nxp.com/t5/S32G/S32G274-SPI-clock-phase-configuration/m-p/2027191#M12319</link>
      <description>&lt;P&gt;Hello,&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/218312"&gt;@Apopo&lt;/a&gt;&amp;nbsp;&lt;BR /&gt;Thanks for your post.&lt;/P&gt;
&lt;P&gt;From my understanding, the settings you have made is actually&amp;nbsp;&lt;SPAN&gt;CPOL=0, CPHA=1.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;If you want to set with&amp;nbsp;CPOL=0, CPHA=0, then the following settings for your reference.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="chenyin_h_0-1736822615793.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/319396iAEB071FE8265B586/image-size/medium?v=v2&amp;amp;px=400" role="button" title="chenyin_h_0-1736822615793.png" alt="chenyin_h_0-1736822615793.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;I hope it will help.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Chenyin&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 14 Jan 2025 02:45:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/S32G274-SPI-clock-phase-configuration/m-p/2027191#M12319</guid>
      <dc:creator>chenyin_h</dc:creator>
      <dc:date>2025-01-14T02:45:10Z</dc:date>
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