Accessing DDR memory controller from M7 cores

maboeln11 — Mon, 11 Nov 2024 19:58:23 GMT

is the length of the DDR registers dependent on the memory size? for example, if the DDR memory size is above 2GB, then all DDR registers or some of them must be 64-bit? in that case are these registers accessible from the M7 cores? does these registers require atomic access? if so, is there a way to mitigate this?

topic Accessing DDR memory controller from M7 cores in S32G

Accessing DDR memory controller from M7 cores