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    <title>S32GのトピックRe: Questions regarding multi-core networking in S32G399A</title>
    <link>https://community.nxp.com/t5/S32G/Questions-regarding-multi-core-networking-in-S32G399A/m-p/1974887#M11270</link>
    <description>&lt;P&gt;Hello &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/24163"&gt;@chenyin_h&lt;/a&gt; ,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;That's good to know that this setup is supported.&lt;/P&gt;&lt;P&gt;Then I will read the documentation about PFE Master/Slave configuration, try to enable this feature and if I face some issue I may open a new topic.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you for your support,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Guilherme&lt;/P&gt;</description>
    <pubDate>Wed, 16 Oct 2024 07:01:57 GMT</pubDate>
    <dc:creator>GuilhermeS32G</dc:creator>
    <dc:date>2024-10-16T07:01:57Z</dc:date>
    <item>
      <title>Questions regarding multi-core networking in S32G399A</title>
      <link>https://community.nxp.com/t5/S32G/Questions-regarding-multi-core-networking-in-S32G399A/m-p/1973875#M11229</link>
      <description>&lt;P&gt;Dear NXP fellows,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I am investigating how to setup the network interfaces of our S32G399A-RDB3 based custom board. This board uses BSP 41.0.&lt;/P&gt;&lt;P&gt;Actually, there are 3 PFE interfaces available:&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;PFE_MAC0: Connected through SGMII to the SJA1110A switch port 4;&lt;/LI&gt;&lt;LI&gt;PFE_MAC1: Connected through RGMII-ID to a 1000BASE-T1 PHY;&lt;/LI&gt;&lt;LI&gt;PFE_MAC2: Connected through RGMII-ID to a 1000BASE-T1 PHY.&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;All of these interfaces are up and running. I can assign IP addresses in different subnets for each of them and I am able to ping my laptop connected through an adapter and vice-versa.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;When I took a look at one internal requirement for the configuration of the IP addresses and VLAN IDs, I saw this specification:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;LI-CODE lang="markup"&gt;Server				Server IP	   VLAN ID        Port
S32G_Mcore			192.168.10.10	10			50102
S32G_Mcore			192.168.12.10	12			50102
S32G_Mcore			192.168.13.10	13			50102
S32G_Mcore			192.168.14.10	14			50102

S32G_Acore			192.168.10.11	10			50101
S32G_Acore			192.168.11.11	11			50101
S32G_Acore			192.168.12.11	12			50101
S32G_Acore			192.168.13.11	13			50101
S32G_Acore			192.168.14.11	14			50101&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;In this case there are a total of five subnets:&lt;/P&gt;&lt;P&gt;192.168.10.X, 192.168.11.X, 192.168.12.X, 192.168.13.X, and 192.168.14.X&lt;/P&gt;&lt;P&gt;And there are different IP addresses for the S32G M7-core and the A53 core.&lt;/P&gt;&lt;P&gt;All of the subnet masks are 255.255.255.0.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;How can I assign a different IP address for M-core and A-core? Does it imply using PFE Master-Slave configuration?&lt;/P&gt;&lt;P&gt;Can our board fulfill this specification?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you very much for the support.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Guilherme&lt;/P&gt;</description>
      <pubDate>Tue, 15 Oct 2024 05:25:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Questions-regarding-multi-core-networking-in-S32G399A/m-p/1973875#M11229</guid>
      <dc:creator>GuilhermeS32G</dc:creator>
      <dc:date>2024-10-15T05:25:04Z</dc:date>
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    <item>
      <title>Re: Questions regarding multi-core networking in S32G399A</title>
      <link>https://community.nxp.com/t5/S32G/Questions-regarding-multi-core-networking-in-S32G399A/m-p/1974861#M11267</link>
      <description>&lt;P&gt;Hello, &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/241130"&gt;@GuilhermeS32G&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks for your post.&lt;/P&gt;
&lt;P&gt;From the description, from my opinion, you could try the PFE master/slave example(M core master/A core slave for example). And then create vlan based on differnt emacX for both M&amp;amp;A core side according to your requirement. I think it is possible and supported.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Chenyin&lt;/P&gt;</description>
      <pubDate>Wed, 16 Oct 2024 06:30:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Questions-regarding-multi-core-networking-in-S32G399A/m-p/1974861#M11267</guid>
      <dc:creator>chenyin_h</dc:creator>
      <dc:date>2024-10-16T06:30:11Z</dc:date>
    </item>
    <item>
      <title>Re: Questions regarding multi-core networking in S32G399A</title>
      <link>https://community.nxp.com/t5/S32G/Questions-regarding-multi-core-networking-in-S32G399A/m-p/1974887#M11270</link>
      <description>&lt;P&gt;Hello &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/24163"&gt;@chenyin_h&lt;/a&gt; ,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;That's good to know that this setup is supported.&lt;/P&gt;&lt;P&gt;Then I will read the documentation about PFE Master/Slave configuration, try to enable this feature and if I face some issue I may open a new topic.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you for your support,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Guilherme&lt;/P&gt;</description>
      <pubDate>Wed, 16 Oct 2024 07:01:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Questions-regarding-multi-core-networking-in-S32G399A/m-p/1974887#M11270</guid>
      <dc:creator>GuilhermeS32G</dc:creator>
      <dc:date>2024-10-16T07:01:57Z</dc:date>
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