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    <title>topic Re: Enabling HSE on A53 core in S32G</title>
    <link>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1973944#M11233</link>
    <description>&lt;P&gt;In your environment, when executing the command "ls /yocto-s32g3/folder", the returned result is "HSE_FW_S32G2XX_0_2_22_0". Inside the path "/yocto-s32g3/folder/hse/bin", the firmware file is as follows: rev1.1_s32g3xx_hse_fw_0.20.0_2.22.0_pb230810.bin.pink.&lt;BR /&gt;For this purpose, please add a line "HSE_SOC_REV = "rev1.1"" in the local.conf file.&lt;/P&gt;</description>
    <pubDate>Tue, 15 Oct 2024 06:54:36 GMT</pubDate>
    <dc:creator>Celeste_Liu</dc:creator>
    <dc:date>2024-10-15T06:54:36Z</dc:date>
    <item>
      <title>Enabling HSE on A53 core</title>
      <link>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1968557#M11046</link>
      <description>&lt;P&gt;&lt;SPAN&gt;How to enable HSE and perform cyrpto operations like Key generation, encryption/decryption, signature generation/verification? Do you have specific document or steps which tells how to enable HSE and perform Crypto graphic operations on A53 core?&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I have performed followings for enabling HSE on A53 core&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Step1: I have enabled HSE on A53 as per the "chapter 10 - HSE security support " of Linux BSP 40 with all the required configuration and placed HSE firmware in required path as per the document and built the yocto package.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;i have added ,&lt;/P&gt;&lt;P&gt;DISTRO_FEATURES:append = " hse "&lt;BR /&gt;NXP_FIRMWARE_LOCAL_DIR = "/yocto-s32/hse"&lt;/P&gt;&lt;P&gt;in local.conf&amp;nbsp;&lt;/P&gt;&lt;P&gt;and then enabled hse_nxp_support&amp;nbsp;&lt;/P&gt;&lt;P&gt;and changed the default firmware file.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Step2: In NxP boot I have configured ATF booting and I have generated IVT by enabling eFuse and configuring HSE(HSE backup image) and flashed on to the target. Here A53 core booting is not happening and its stuck in booting and showing that A53 core loaded and reset handler address is 0x34610000&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 08 Oct 2024 06:33:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1968557#M11046</guid>
      <dc:creator>ashwini2024</dc:creator>
      <dc:date>2024-10-08T06:33:48Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling HSE on A53 core</title>
      <link>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1969483#M11072</link>
      <description>&lt;P&gt;Hello&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/234952"&gt;@ashwini2024&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;Thanks for contacting us. We are following this same inquiry with another member of your company, would you like us to mirror the information from the other support case into that one?&lt;/P&gt;
&lt;P&gt;And I notice that you want to enable HSE on the A core. If you only want to enable the A core and don't need the M core, then step 2 is not necessary. IVT is used to generate the image for M core startup, and this operation is not mandatory.&lt;/P&gt;
&lt;P&gt;As for your question about enabling HSE and performing crypto operations like key generation, encryption/decryption, and signature generation/verification on the A53 core, I recommend referring to documents AN13495 and AN14072. These two documents describe in detail how to access HSE using PKCS#11 in the A53 core.&amp;nbsp;I have already sent these documents to your colleague through the SFDC platform.&lt;/P&gt;
&lt;P&gt;If you have any further questions or need more assistance, please feel free to let us know.&lt;/P&gt;
&lt;P&gt;Best Regards,&lt;/P&gt;
&lt;P&gt;Celeste&lt;/P&gt;</description>
      <pubDate>Wed, 09 Oct 2024 04:24:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1969483#M11072</guid>
      <dc:creator>Celeste_Liu</dc:creator>
      <dc:date>2024-10-09T04:24:23Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling HSE on A53 core</title>
      <link>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1969614#M11076</link>
      <description>&lt;P&gt;I am using bsp 40.&lt;BR /&gt;In order to enable hse On the A53 core i have included the below lines in local.conf:&lt;BR /&gt;&lt;SPAN&gt;&lt;SPAN class=""&gt;DISTRO_FEATURES:append = " hse "&lt;BR /&gt;NXP_FIRMWARE_LOCAL_DIR = "/yocto-s32g3/hse" [I have created a hse folder and placed the HSE_FW_S32G3XX_0_2_22_0 folder provided by NXP]&lt;BR /&gt;HSE_VERSION = "0_2_22_0"&lt;BR /&gt;HSE_SOC_REV = "rev1.0"&lt;BR /&gt;HSE_LIC_MD5 = "a1bda359fc5cdcfca04f84834841a5ca"&lt;BR /&gt;Then i have enabled NXP_HSE_SUPPORT :&lt;BR /&gt;CONFIG_NXP_HSE_SUPPORT=y&lt;BR /&gt;CONFIG_NXP_HSE_FW_FILE="/yocto-s32g3/build_s32g399ardb3/tmp/work/s32g399ardb3-fsl-linux/u-boot-s32/2022.04-r0/recipe-sysroot/lib/firmware/s32cc_hse_fw.bin"&lt;BR /&gt;&lt;BR /&gt;Now a log_do_compile file is generated with the image layout as follows:&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Image Layout&lt;BR /&gt;  DCD:      Offset: 0x200    Size: 0x1c&lt;BR /&gt;  IVT:      Offset: 0x1000    Size: 0x100&lt;BR /&gt;  HSE Firmware:    Offset: 0x1200    &lt;BR /&gt;  HSE SYS Image:    Offset: 0x62400    Size: 0xc000&lt;BR /&gt;  AppBootCode Header:  Offset: 0x6e400    Size: 0x40&lt;BR /&gt;  Application:    Offset: 0x6e440    Size: 0x2f800&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Boot Core:  A53_0&lt;BR /&gt;IVT Location:  SD/eMMC&lt;BR /&gt;Load address:  0x346062c0&lt;BR /&gt;Entry point:  0x34610000&lt;/P&gt;&lt;P&gt;While creating blob we have placed hse at 0x1200 and hse sys image at 0x6400 then updated load address as 0x346062c0 as in&amp;nbsp; the log do compile image layout and even the reset handler address is updated to 0x34610000 Source address in QSPI as 0x601240 and load address in RAM as 0x34606b00.&lt;BR /&gt;I have copied the kernel image , rootfs and dtb file to the SD card.&lt;BR /&gt;I have flashed the IVT blob, the fip.s32-sdcard.&lt;BR /&gt;I am getting the below error the control is not going to the atf and it is stuck at the reset handler.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ashwini2024_0-1728456868786.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/303657i569C34D56BE53218/image-size/medium?v=v2&amp;amp;px=400" role="button" title="ashwini2024_0-1728456868786.png" alt="ashwini2024_0-1728456868786.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;What is the fault and Are there any modifications or should i add any support on the yocto side ?&lt;BR /&gt;Please do reply.&lt;BR /&gt;Thank you.&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN class=""&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 09 Oct 2024 07:01:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1969614#M11076</guid>
      <dc:creator>ashwini2024</dc:creator>
      <dc:date>2024-10-09T07:01:19Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling HSE on A53 core</title>
      <link>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1969626#M11078</link>
      <description>&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ashwini2024_0-1728457968905.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/303660i42D00D5AB3CB91BB/image-size/medium?v=v2&amp;amp;px=400" role="button" title="ashwini2024_0-1728457968905.png" alt="ashwini2024_0-1728457968905.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;this is the blob structure&lt;/P&gt;</description>
      <pubDate>Wed, 09 Oct 2024 07:13:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1969626#M11078</guid>
      <dc:creator>ashwini2024</dc:creator>
      <dc:date>2024-10-09T07:13:27Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling HSE on A53 core</title>
      <link>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1969865#M11094</link>
      <description>&lt;P&gt;If i have to enable hse on A53 core alone without nor flash and by using sd card boot mode what steps should i follow ? Should i update the dts file to change the memory reserved for hse ?&lt;BR /&gt;Please do reply.&lt;/P&gt;</description>
      <pubDate>Wed, 09 Oct 2024 10:51:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1969865#M11094</guid>
      <dc:creator>ashwini2024</dc:creator>
      <dc:date>2024-10-09T10:51:38Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling HSE on A53 core</title>
      <link>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1969897#M11099</link>
      <description>&lt;P&gt;Sorry for the late reply. I have a lot of work on hand and have limited bandwidth.&lt;BR /&gt;If you only want to enable HSE only on the A53 core with SD card boot mode. After editing the conf/local.conf file, you can directly use Yocto build and use the command "bitbake fsl-image-auto" to compile and generate the *.sdcard file. It can be found in the build_s32g274aevb/tmp/deploy/images/s32g274aevb directory. After burning the image to the RDB2 board, the boot-up print is as shown below.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Celeste_Liu_0-1728472856183.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/303744iA4C444A7AA457815/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Celeste_Liu_0-1728472856183.png" alt="Celeste_Liu_0-1728472856183.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;Thank you for your understanding.&lt;/P&gt;</description>
      <pubDate>Wed, 09 Oct 2024 11:21:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1969897#M11099</guid>
      <dc:creator>Celeste_Liu</dc:creator>
      <dc:date>2024-10-09T11:21:44Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling HSE on A53 core</title>
      <link>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1969920#M11100</link>
      <description>&lt;P&gt;I am not getting any logs while doing the changes.&lt;BR /&gt;In local.conf i have added the following :&lt;BR /&gt;&lt;SPAN&gt;&lt;SPAN class=""&gt;DISTRO_FEATURES:append = " hse "&lt;BR /&gt;NXP_FIRMWARE_LOCAL_DIR = "/yocto-s32g3/hse"&lt;BR /&gt;HSE_VERSION = "0_2_22_0"&lt;BR /&gt;HSE_SOC_REV = "rev1.0"&lt;BR /&gt;HSE_LIC_MD5 = "a1bda359fc5cdcfca04f84834841a5ca"&lt;BR /&gt;&lt;BR /&gt;what am i supposed to update in local.conf?&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 09 Oct 2024 12:03:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1969920#M11100</guid>
      <dc:creator>ashwini2024</dc:creator>
      <dc:date>2024-10-09T12:03:07Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling HSE on A53 core</title>
      <link>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1970842#M11118</link>
      <description>&lt;P&gt;I am using bsp 40. The board is s32g399ardb3.&lt;BR /&gt;Could you let me know what are the changes to be included in the local.conf?&lt;/P&gt;</description>
      <pubDate>Thu, 10 Oct 2024 03:02:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1970842#M11118</guid>
      <dc:creator>ashwini2024</dc:creator>
      <dc:date>2024-10-10T03:02:45Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling HSE on A53 core</title>
      <link>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1971135#M11127</link>
      <description>&lt;P&gt;&lt;SPAN&gt;In local.conf, You can only add the following three lines:&lt;/SPAN&gt;&lt;/P&gt;
&lt;LI-CODE lang="markup"&gt;DISTRO_FEATURES:append = " hse "
NXP_FIRMWARE_LOCAL_DIR = "/yocto-s32g3/hse"
HSE_VERSION = "0_2_22_0"&lt;/LI-CODE&gt;
&lt;P&gt;Please note that this must be the content of the folder pointed by NXP_FIRMWARE_LOCAL_DIR:&lt;/P&gt;
&lt;LI-CODE lang="javascript"&gt;ls /yocto-s32g3/hse
HSE_FW_S32G3XX_0_2_22_0&lt;/LI-CODE&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 10 Oct 2024 07:55:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1971135#M11127</guid>
      <dc:creator>Celeste_Liu</dc:creator>
      <dc:date>2024-10-10T07:55:10Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling HSE on A53 core</title>
      <link>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1971314#M11131</link>
      <description>&lt;P&gt;Thank you for your prompt reply. Are there any changes to be done further for changing the reserved memory space for hse in dts files?&lt;/P&gt;</description>
      <pubDate>Thu, 10 Oct 2024 11:10:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1971314#M11131</guid>
      <dc:creator>ashwini2024</dc:creator>
      <dc:date>2024-10-10T11:10:39Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling HSE on A53 core</title>
      <link>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1971809#M11139</link>
      <description>&lt;P&gt;We recommend using the command "bitbake fsl-image-auto" to compile and generate the *.sdcard file. It does not require modifying the DTS files.&lt;/P&gt;</description>
      <pubDate>Fri, 11 Oct 2024 03:08:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1971809#M11139</guid>
      <dc:creator>Celeste_Liu</dc:creator>
      <dc:date>2024-10-11T03:08:28Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling HSE on A53 core</title>
      <link>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1973889#M11231</link>
      <description>&lt;P&gt;I am using bitbake ros-image-core and not bitbake fsl-image-core Any changes required?&lt;/P&gt;</description>
      <pubDate>Tue, 15 Oct 2024 05:49:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1973889#M11231</guid>
      <dc:creator>ashwini2024</dc:creator>
      <dc:date>2024-10-15T05:49:00Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling HSE on A53 core</title>
      <link>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1973909#M11232</link>
      <description>&lt;P&gt;The following is my local.conf file :&lt;/P&gt;&lt;P&gt;MACHINE ??= 's32g399ardb3'&lt;BR /&gt;DISTRO ?= 'fsl-auto'&lt;BR /&gt;PACKAGE_CLASSES ?= "package_deb"&lt;BR /&gt;IMAGE_FEATURES += "package-management"&lt;BR /&gt;EXTRA_IMAGE_FEATURES ?= "debug-tweaks"&lt;BR /&gt;USER_CLASSES ?= "buildstats"&lt;BR /&gt;PATCHRESOLVE = "noop"&lt;BR /&gt;BB_DISKMON_DIRS ??= "\&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; STOPTASKS,${TMPDIR},1G,100K \&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; STOPTASKS,${DL_DIR},1G,100K \&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; STOPTASKS,${SSTATE_DIR},1G,100K \&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; STOPTASKS,/tmp,100M,100K \&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; HALT,${TMPDIR},100M,1K \&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; HALT,${DL_DIR},100M,1K \&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; HALT,${SSTATE_DIR},100M,1K \&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; HALT,/tmp,10M,1K"&lt;BR /&gt;PACKAGECONFIG:append:pn-qemu-system-native = " sdl"&lt;BR /&gt;CONF_VERSION = "2"&lt;BR /&gt;BB_NUMBER_THREADS = "4"&lt;BR /&gt;PARALLEL_MAKE = "-j 4"&lt;BR /&gt;DL_DIR = "/yocto-s32g3/downloads"&lt;BR /&gt;SSTATE_DIR = "/yocto-s32g3/sstate-cache"&lt;BR /&gt;ACCEPT_FSL_EULA = ""&lt;BR /&gt;LICENSE_FLAGS_ACCEPTED:append = " commercial_elektrobit"&lt;BR /&gt;GCCVERSION = "11.%"&lt;BR /&gt;GCC_DISABLE_LANGUAGES = "fortran"&lt;BR /&gt;EXTRA_OECONF:append_pn-gcc = " --disable-languages=fortran"&lt;BR /&gt;EXTRA_OECONF:appen_pn-gcc-corss = " --disable-languages=fortran"&lt;BR /&gt;DISTRO_FEATURES:append = " virtualization "&lt;BR /&gt;DISTRO_FEATURES:append = " lxc"&lt;BR /&gt;PREFERRED_VERSION_linux-s32 = "6.6.12"&lt;BR /&gt;IMAGE_INSTALL += "modemmanager"&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;# Parallelism Options&lt;BR /&gt;BB_NUMBER_THREADS = "8"&lt;BR /&gt;PARALLEL_MAKE = "-j 8"&lt;BR /&gt;DL_DIR = "/yocto-s32g3/downloads"&lt;BR /&gt;SSTATE_DIR = "/yocto-s32g3/sstate-cache"&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;DISTRO_FEATURES:append = " hse "&lt;BR /&gt;NXP_FIRMWARE_LOCAL_DIR = "/yocto-s32g3/folder"&lt;BR /&gt;HSE_VERSION="0_2_22_0"&lt;/P&gt;&lt;P&gt;Inside my /folder/hse/bin the fw file is as follows:&lt;/P&gt;&lt;P&gt;rev1.0_s32g3xx_hse_fw_0.20.0_2.22.0_pb230821.bin.pink&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;Now when i do bitbake ros-image-core and generate the .sdcard file and copy it and flash on the target machine and do sd card boot ,&lt;BR /&gt;i am not getting any logs and the output is as below displayed in the image.&lt;BR /&gt;Please let me know where i am doing an error .&lt;BR /&gt;THank you.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ashwini2024_0-1728973205986.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/304675i8454E606E2CA48D4/image-size/medium?v=v2&amp;amp;px=400" role="button" title="ashwini2024_0-1728973205986.png" alt="ashwini2024_0-1728973205986.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 15 Oct 2024 06:20:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1973909#M11232</guid>
      <dc:creator>ashwini2024</dc:creator>
      <dc:date>2024-10-15T06:20:39Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling HSE on A53 core</title>
      <link>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1973944#M11233</link>
      <description>&lt;P&gt;In your environment, when executing the command "ls /yocto-s32g3/folder", the returned result is "HSE_FW_S32G2XX_0_2_22_0". Inside the path "/yocto-s32g3/folder/hse/bin", the firmware file is as follows: rev1.1_s32g3xx_hse_fw_0.20.0_2.22.0_pb230810.bin.pink.&lt;BR /&gt;For this purpose, please add a line "HSE_SOC_REV = "rev1.1"" in the local.conf file.&lt;/P&gt;</description>
      <pubDate>Tue, 15 Oct 2024 06:54:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1973944#M11233</guid>
      <dc:creator>Celeste_Liu</dc:creator>
      <dc:date>2024-10-15T06:54:36Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling HSE on A53 core</title>
      <link>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1973948#M11234</link>
      <description>&lt;P&gt;Why should i use rev 1.1 and not rev 1.0 ?&lt;/P&gt;</description>
      <pubDate>Tue, 15 Oct 2024 07:05:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1973948#M11234</guid>
      <dc:creator>ashwini2024</dc:creator>
      <dc:date>2024-10-15T07:05:30Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling HSE on A53 core</title>
      <link>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1973951#M11235</link>
      <description>&lt;P&gt;The command for copying the file i am using is :&lt;SPAN&gt;&lt;SPAN class=""&gt;sudo dd if=./ros-image-core-foxy-s32g399ardb3-20241015060613.rootfs.sdcard of=/dev/sda status=progress &amp;amp;&amp;amp; sync&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 15 Oct 2024 07:07:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1973951#M11235</guid>
      <dc:creator>ashwini2024</dc:creator>
      <dc:date>2024-10-15T07:07:06Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling HSE on A53 core</title>
      <link>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1974090#M11240</link>
      <description>&lt;P&gt;See the description in the document "Release Notes for S32G3 HSE Firmware 0.2.22.0".&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Celeste_Liu_0-1728982741737.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/304736i5B93AFC51A79048D/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Celeste_Liu_0-1728982741737.png" alt="Celeste_Liu_0-1728982741737.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 15 Oct 2024 08:59:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1974090#M11240</guid>
      <dc:creator>Celeste_Liu</dc:creator>
      <dc:date>2024-10-15T08:59:14Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling HSE on A53 core</title>
      <link>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1974121#M11242</link>
      <description>&lt;P&gt;There is no content about bitbake ros-image-core in the Linux BSP document. You can refer to &lt;A href="https://community.nxp.com/t5/S32G/bitbake-stuck/td-p/1879012" target="_blank"&gt;bitbake stuck - NXP Community&lt;/A&gt;. We apologize for the inconvenience caused.&lt;/P&gt;</description>
      <pubDate>Tue, 15 Oct 2024 09:15:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1974121#M11242</guid>
      <dc:creator>Celeste_Liu</dc:creator>
      <dc:date>2024-10-15T09:15:10Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling HSE on A53 core</title>
      <link>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1974140#M11243</link>
      <description>&lt;P&gt;Does that mean i can use any version or is it board dependent ?&lt;/P&gt;</description>
      <pubDate>Tue, 15 Oct 2024 09:24:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1974140#M11243</guid>
      <dc:creator>ashwini2024</dc:creator>
      <dc:date>2024-10-15T09:24:15Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling HSE on A53 core</title>
      <link>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1974158#M11244</link>
      <description>&lt;P&gt;&lt;SPAN&gt;It is board dependent. It can be seen from the startup print information of U-boot. On my side, the screenshot is as follows.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Celeste_Liu_0-1728984946595.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/304759i00F8DADAEC2A0B7C/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Celeste_Liu_0-1728984946595.png" alt="Celeste_Liu_0-1728984946595.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 15 Oct 2024 09:36:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Enabling-HSE-on-A53-core/m-p/1974158#M11244</guid>
      <dc:creator>Celeste_Liu</dc:creator>
      <dc:date>2024-10-15T09:36:29Z</dc:date>
    </item>
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