About pinctrl Device Tree Bindings and PINMUX

GuilhermeS32G3 — Thu, 05 Sep 2024 05:48:57 GMT

Dear NXP fellows,

This questions is related to my previous question.

I would like to get a better understanding of the pin mux and how does it relate the hardware pin to the device tree mapping.

Let's suppose I am using S32G274ARDB board with BSP35.0.

When I look at the schematic design file of the board I see that it uses the PFE_MAC2 to connect to the Micrel KSZ9031 Phy Device through RGMII:

So, if I look at the schematic of the KSZ9031 device, I see that its pin 25 (TX_EN) is connected to the signal RGMIIB_TXC, which corresponds to the pin V20 (PFE_MAC2_TX_CLK) of the P32G274AABK1VUCT:

Ok, so if I take a look at the Kernel device tree file s32gxxxx.dtsi, I see that the pfe_netif2 (PFE_MAC2) is using phy-handle = <&pfe_mdio_b_phy4> or ethernet-phy@4 and pfe2rgmiib_pins is defined in the following way:

pfe2rgmiib_pins: pfe2rgmiib_pins { pfe2rgmiib_grp0 { pinmux = <S32CC_PINMUX(78, FUNC2)>, <S32CC_PINMUX(144, FUNC2)>, <S32CC_PINMUX(113, FUNC2)>, <S32CC_PINMUX(114, FUNC2)>, <S32CC_PINMUX(115, FUNC2)>; output-enable; slew-rate = <S32CC_FAST_SLEW_166MHZ>; }; pfe2rgmiib_grp1 { pinmux = <S32CC_PINMUX(116, FUNC0)>, <S32CC_PINMUX(117, FUNC0)>, <S32CC_PINMUX(118, FUNC0)>, <S32CC_PINMUX(119, FUNC0)>, <S32CC_PINMUX(120, FUNC0)>, <S32CC_PINMUX(121, FUNC0)>; input-enable; slew-rate = <S32CC_FAST_SLEW_166MHZ>; }; pfe2rgmiib_grp2 { pinmux = <S32CC_PINMUX(879, FUNC3)>, <S32CC_PINMUX(885, FUNC3)>, <S32CC_PINMUX(881, FUNC3)>, <S32CC_PINMUX(882, FUNC3)>, <S32CC_PINMUX(883, FUNC3)>, <S32CC_PINMUX(884, FUNC3)>, <S32CC_PINMUX(886, FUNC3)>; }; pfe2rgmiib_grp3 { pinmux = <S32CC_PINMUX(122, FUNC2)>; output-enable; slew-rate = <S32CC_FAST_SLEW_166MHZ>; bias-pull-up; }; };

Ok, from the file s32cc-pinfunc.h I see that the S32CC_PINMUX function is defined as follows:

#define FUNC0 0 #define FUNC1 1 #define FUNC2 2 #define FUNC3 3 #define FUNC4 4 #define FUNC5 5 #define FUNC6 6 #define FUNC7 7 #define S32CC_PINMUX(PIN, FUNC) (((PIN) << 4) | (FUNC))

Ok, so from an external repository, I found that definition:

#define S32_G274_PAD_PH10__PFE2_TXCLK_IN 886 PAD_CTL_SRC_SIG_SEL3

That means the PIN 886 corresponds to PH10__PFE2_TXCLK_IN.

And my questions are:

Where does this number 886 comes from? Is there a documentation somewhere that associates this number with a specific pin in the hardware?
What is the meaning of FUNC0, FUNC1, FUNC2, etc.?
If in my custom board design I decide to replace Micrel KSZ9031 Phy Device by a Marvell Phy Device, can I still use the same pfe2rgmiib_pins or I need to adapt it to the current hardware?

Thank you very much for your support,

Best regards,

Guilherme

Re: About pinctrl Device Tree Bindings and PINMUX

chenyin_h — Mon, 09 Sep 2024 07:56:21 GMT

Hello, @GuilhermeS32G3

Sorry for the delay.

You may find it in S32G2/3 RM, specially, S32G_IOMUX attached to the RM hold more information on it.
It could be found also in the document above, simply mean different settings.
You may carefully reference the datasheet of the new phy, it is possible that the pin settings you mentioned need to be modified in order to adapt to the new hardware.

Chenyin

topic Re: About pinctrl Device Tree Bindings and PINMUX in S32G

About pinctrl Device Tree Bindings and PINMUX

Re: About pinctrl Device Tree Bindings and PINMUX