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    <title>topic Re: Core Access to Peripherals in NXP S32G3 (Cortex-A and Cortex-M) in S32G</title>
    <link>https://community.nxp.com/t5/S32G/Core-Access-to-Peripherals-in-NXP-S32G3-Cortex-A-and-Cortex-M/m-p/1932635#M10209</link>
    <description>&lt;P&gt;Hello, &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/234583"&gt;@AhmedAbd-ElFattah&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks for your post.&lt;/P&gt;
&lt;P&gt;As far as I know, all peripherals could be accssed by both kinds of cores.(M&amp;amp;A)&lt;/P&gt;
&lt;P&gt;You may reference the S32G3 reference manual for details.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Chenyin&lt;/P&gt;</description>
    <pubDate>Thu, 15 Aug 2024 02:45:46 GMT</pubDate>
    <dc:creator>chenyin_h</dc:creator>
    <dc:date>2024-08-15T02:45:46Z</dc:date>
    <item>
      <title>Core Access to Peripherals in NXP S32G3 (Cortex-A and Cortex-M)</title>
      <link>https://community.nxp.com/t5/S32G/Core-Access-to-Peripherals-in-NXP-S32G3-Cortex-A-and-Cortex-M/m-p/1931766#M10195</link>
      <description>&lt;DIV class=""&gt;&lt;DIV&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;P&gt;I need information on which cores (Cortex-A or Cortex-M) can access each peripheral in the NXP S32G3. For instance, whether the RTC can be accessed by Cortex-A, Cortex-M, or both. Is there a document that contains this information?&lt;BR /&gt;&lt;BR /&gt;Thanks a lot in advance&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Wed, 14 Aug 2024 07:50:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Core-Access-to-Peripherals-in-NXP-S32G3-Cortex-A-and-Cortex-M/m-p/1931766#M10195</guid>
      <dc:creator>AhmedAbd-ElFattah</dc:creator>
      <dc:date>2024-08-14T07:50:13Z</dc:date>
    </item>
    <item>
      <title>Re: Core Access to Peripherals in NXP S32G3 (Cortex-A and Cortex-M)</title>
      <link>https://community.nxp.com/t5/S32G/Core-Access-to-Peripherals-in-NXP-S32G3-Cortex-A-and-Cortex-M/m-p/1932635#M10209</link>
      <description>&lt;P&gt;Hello, &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/234583"&gt;@AhmedAbd-ElFattah&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks for your post.&lt;/P&gt;
&lt;P&gt;As far as I know, all peripherals could be accssed by both kinds of cores.(M&amp;amp;A)&lt;/P&gt;
&lt;P&gt;You may reference the S32G3 reference manual for details.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Chenyin&lt;/P&gt;</description>
      <pubDate>Thu, 15 Aug 2024 02:45:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32G/Core-Access-to-Peripherals-in-NXP-S32G3-Cortex-A-and-Cortex-M/m-p/1932635#M10209</guid>
      <dc:creator>chenyin_h</dc:creator>
      <dc:date>2024-08-15T02:45:46Z</dc:date>
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