Power Management中的主题 Re: i.MX6 startup sequence

i.MX6 startup sequence

孙金凯 — Tue, 23 Jul 2019 04:29:13 GMT

What's the LDOs（VDDARM_CAP 、VDDSOC_CAP、VDDHIGH_CAP） start-up sequence within i.mx6 ？

Is the POR_B signal first or LDOs output first？

Re: i.MX6 startup sequence

reyes — Tue, 23 Jul 2019 20:30:55 GMT

Hi,

That depends on the version of the i.MX6 and the version of the PMIC you are using, for example, if you are using the i.MX6Q, you should use the MMPF0100F0AEP version of the PMIC as you can see in Table 1 of the MMPF0100 PMIC datasheet: https://www.nxp.com/docs/en/data-sheet/MMPF0100.pdf

Now, if you check Table 10 of the same PMIC datasheet, you can find the start-up sequence configuration for all the regulators.

And from the I.MX6 point of view, you can typically find the requirements of the power up sequence in the device datasheet, for example, in section 4.2.1 of the i.MX6Q datasheet (https://www.nxp.com/docs/en/data-sheet/IMX6DQCEC.pdf), you can find the following sentence:

For power-up sequence, the restrictions are as follows:

VDD_SNVS_IN supply must be turned ON before any other power supply. It may be connected (shorted) with VDD_HIGH_IN supply.
If a coin cell is used to power VDD_SNVS_IN, then ensure that it is connected before any other supply is switched on.
The SRC_POR_B signal controls the processor POR and must be immediately asserted at power-up and remain asserted until the VDD_ARM_CAP, VDD_SOC_CAP, and VDD_PU_CAP supplies are stable. VDD_ARM_IN and VDD_SOC_IN may be applied in either order with no restrictions.

Regards,

Jose

Re: i.MX6 startup sequence

孙金凯 — Thu, 25 Jul 2019 03:59:10 GMT

Thank you，Jose！

But my board (2/4) can't startup,and I added 400ms delay before POR.

The LDOs has no output and the clock（32K） did not oscillate.

i.MX6DL and MMPF0100F0AZES

Re: i.MX6 startup sequence

reyes — Thu, 25 Jul 2019 16:58:57 GMT

Hi,

I’m not sure if I’m properly understanding, but when you mention “my board (2/4) can't startup” you are saying that 2 of 4 of your boards are presenting this same issue? Please confirm, this could be important and could tell us that there are no problems with the design, but with the part itself (like a quality problem) or manufacture issue (like soldering profile).

You also mentioned “The LDOs has no output”, please confirm which LDO you are referring to.

It is also important to know the HW configuration of the VDDOTP pin, connecting the VDDOTP pin to VCOREDIG through a 100 kΩ resistor. And using this configuration, LDOs VGEN1 and VGEN 3 are disabled as you can see in Table 9 of the datasheet: https://www.nxp.com/docs/en/data-sheet/MMPF0100Z.pdf

Re: i.MX6 startup sequence

孙金凯 — Fri, 26 Jul 2019 02:17:12 GMT

Hi，Jose

If a quality problem，please confirm the reason and What part of it might have caused it?

“The LDOs has no output”——VDDARM_CAP 、VDDSOC_CAP、VDDHIGH_CAP，32K and 24Mhz can't start too！

the VDDOTP pin followed evaluation board “MCIMX6DL-SDP”.

Re: i.MX6 startup sequence

reyes — Mon, 29 Jul 2019 15:43:14 GMT

Hi,

Quality problems are rare and typically affects more complete lots, this is why I asked to clarify your “my board (2/4) can't startup” comment, are you saying that 2 of 4 of your boards are presenting this same issue? Please confirm, this could be important and could tell us that there are no problems with the design, but with the part itself (like a quality problem) or manufacture issue (like soldering profile).

VCOREDIG hardware pin configuration is correct.

Only one 22 mF bulk capacitor should be connected to each of these on-chip LDO regulator outputs:

VDD_ARM_CAP
VDD_SOC_CAP

If the nominal capacitance value is larger than recommended, power-up ramp time is excessive and operation cannot be guaranteed. Note that the ramp up time is constant. Larger capacitors mean more inrush current. Select small capacitors with low ESR (equivalent series resistance).

Do not connect any loads to these LDO outputs: VDDARM_CAP, VDDARM23_CAP, or VDDPU_CAP. VDDSOC_CAP is restricted to MX6 loads.

Only one 10 mF bulk capacitor should be connected to VDD_HIGH_CA.

If the nominal capacitance value is larger than recommended, power-up ramp time is excessive and operation cannot be guaranteed. Select small capacitors with low ESR.

These LDOs should only be used to power the loads as described in the reference manual or data sheet. Do not connect any loads to these LDO outputs: NVCC_PLL_OUT or VDDUSB_CAP.

VDDHIGH_CAP is restricted to MX6 loads.

Regards,

Jose

NXP Semiconductors

Re: i.MX6 startup sequence

孙金凯 — Tue, 30 Jul 2019 02:46:46 GMT

Are you sure 22mF?

But my reference design is 22uF！

I can give you a answer with the following question YES！

“my board (2/4) can't startup” comment, are you saying that 2 of 4 of your boards are presenting this same issue?

But what part of it might have caused it? i.max6 itself？

Re: i.MX6 startup sequence

reyes — Tue, 30 Jul 2019 17:22:28 GMT

Hi,

You are correct, 22uF is correct.

If only of 4 of your boards are presenting the failure, I don’t think the problem could be related to a quality issue, since this kind of issues are typically affecting the complete batch, so, only if the failure is present on 4 of your 4 boards, we could think in a quality issue.

Quality issue are the ones that are present since the fabric, but this does not seem to be the case.

One thing that I would recommend you to do is a swap to make sure that the problem is with the i.mx6 itself of with the board or with the manufacturing/soldering process. Get a new sample of the i.mx6 or one from another board that you know it is working properly and solder it to a failing board to test it.

Regards,

Jose

NXP Semiconductors

Re: i.MX6 startup sequence

孙金凯 — Fri, 10 Jan 2020 07:34:52 GMT

最终结论是虚焊或者i.MX6损坏造成的，更换i.MX6后正常！