topic Re: Inquiry regarding RDBESS774A3EVB - Board Damage due to Swapped Connectors (J1_1 and J1_3) in Power Management

Inquiry regarding RDBESS774A3EVB - Board Damage due to Swapped Connectors (J1_1 and J1_3)

WcrTh — Mon, 22 Jun 2026 05:04:06 GMT

Hi,

I am currently evaluating the RDBESS774A3EVB Cell Monitoring Unit (CMU) board (which features the MC33774A Battery Cell Controllers) connected to a 50-cell battery pack setup.

Recently, an accidental misconnection occurred during our testing. We mistakenly swapped the cell connector sets between J1_1 (upper set) and J1_3 (lower set).

The following behaviors were observed during the incident:

Initial Event: Immediately upon swapping the connectors, a heavy short circuit occurred at Cell 36, causing an external wire/trace to burn out and break.
Subsequent Action: After discovering the mistake, we reconnected the battery packs to the same board using the correct connector positions.
Secondary Behavior: As soon as the correct connection was established, multiple balancing resistors (R_balance) on the board began to overheat and burn out.

Based on this scenario, we would highly appreciate your engineering insights regarding the following questions:

Q1: Did the initial connector swap between J1_1 and J1_3 cause catastrophic internal damage to the MC33774A ICs or related circuitry during the first event?
Q2: Is it correct to assume that the multiple balancing resistors burning out during the second (correct) connection was a direct consequence of internal damage inside the MC33774A ICs (e.g., internal FET breakdown or gate drivers stuck in an ON-state) caused by the first incident?
Q3: If we replace the damaged MC33774A ICs and all the burned balancing resistors, can the RDBESS774A3EVB board be restored to a fully functional and safe working condition? Are there any other critical companion components (such as ESD/Zener protection diodes or isolation circuit elements) that we should inspect or replace alongside the main ICs?

Re: Inquiry regarding RDBESS774A3EVB - Board Damage due to Swapped Connectors (J1_1 and J1_3)

guoweisun — Mon, 22 Jun 2026 05:36:08 GMT

Do you mean you mistake to add the 50*3.6V voltage between C17 to ground in the MC33774 first part?

Re: Inquiry regarding RDBESS774A3EVB - Board Damage due to Swapped Connectors (J1_1 and J1_3)

WcrTh — Tue, 23 Jun 2026 03:14:35 GMT

Hi @guoweisun,

We did not connect the entire 50-cell pack into a single connector. Instead, our 50-cell system is divided into three separate segments with three distinct cell connectors.

1 Initial Event ERROR: CONNECTOR SWAP2 Subsequent Action: NORMAL CONNECTION

Re: Inquiry regarding RDBESS774A3EVB - Board Damage due to Swapped Connectors (J1_1 and J1_3)

WcrTh — Fri, 26 Jun 2026 06:52:04 GMT

Hi @guoweisun,

To ensure complete hardware safety and prevent any potential wiring issues, we have designed a intermediate "CSU BRIDGE BOARD" to route our 50S battery pack to the RDBESS774A3EVB (featuring three MC33774A AFEs in a daisy chain).

Could you please review our attached schematics (CSUBridge_Connector.png and CSUBridge_Block Diagram.png) and verify if our pin mapping and connection strategy are correct?

Re: Inquiry regarding RDBESS774A3EVB - Board Damage due to Swapped Connectors (J1_1 and J1_3)

guoweisun — Mon, 29 Jun 2026 06:21:17 GMT

Seems no more issue be found but pay attention on the GDN1 GND2 GND3 positions.

Re: Inquiry regarding RDBESS774A3EVB - Board Damage due to Swapped Connectors (J1_1 and J1_3)

WcrTh — Tue, 30 Jun 2026 06:40:04 GMT

Thank you for your ongoing support. First, we would like to clarify the AFE stacking order in our actual hardware setup to ensure we are aligned:

AFE1 (J1_1) is designated for the High-Voltage stage (Cells 37–50).
AFE3 (J1_3) is designated for the Low-Voltage stage (Cells 1–18).

We have attached the image which document our recent findings and the critical issue we are currently facing.

We would appreciate your explicit answers to our previous questions regarding the first incident, as well as a new issue with a new board:

[Part 1: Retrospective Questions on the First Board]

Q1: Did the initial connector swap between J1_1 and J1_3 cause catastrophic internal damage to the MC33774A ICs or related circuitry during that first event?
Q2: Is it correct to assume that the multiple balancing resistors burning out during the second (corrected) connection was a direct consequence of internal damage inside the MC33774A ICs (e.g., internal FET breakdown or gate drivers stuck in an ON-state) caused by the first incident?
Q3: If we replace the damaged MC33774A ICs and all the burned balancing resistors, can the RDBESS774A3EVB board be restored to a fully functional and safe working condition? Are there any other critical companion components (such as ESD/Zener protection diodes or isolation circuit elements) that we should inspect or replace alongside the main ICs?

[Part 2: NEW ISSUE with a New Board]

Following the correct stacking order mentioned above (High-Voltage to AFE1/J1_1, Low-Voltage to AFE3/J1_3), we attempted to test our system using a completely new RDBESS774A3EVB board.

However, as soon as it was connected, smoke occurred immediately, and the balancing IC (MC33774A) on the High-Voltage segment (Cells 37–50 / AFE1) was damaged once again.

Given that the connection was mapped exactly as intended (High-to-High, Low-to-Low), could you please help us analyze why the new board failed instantly at the AFE1 stage?

Re: Inquiry regarding RDBESS774A3EVB - Board Damage due to Swapped Connectors (J1_1 and J1_3)

WcrTh — Thu, 09 Jul 2026 09:01:12 GMT

Hi @guoweisun ,

We are currently encountering a severe issue where the balancing IC is getting damaged during the sequential connection of multiple battery cell groups.

Following the local NXP technical advice regarding the unused channels on our Group 1 section (which monitors 14 cells), we have terminated the unused pins as follows directly at the balancing IC input:

Connected CB15-18 shorted to CB14
Connected CT15-18 shorted to CT14

Here are the details of our test procedures and the corresponding outcomes:

Test 1: Single Group Connection (Group 1 Only)
Procedure: We connected only Group 1, which corresponds to the highest potential segment: Cell 37 to Cell 50 (Total of 14 cells, total voltage approx. 50V).

Result: The board functioned normally. We were able to accurately read the voltages of all cells. The measured voltage of VBAT_1 relative to GND_1 was stable at approximately 50V. No anomalies were observed.

Test 2: Full 3-Group Connection (Sequential Power-Up)
Procedure: We connected all 3 cell groups simultaneously but followed a strict bottom-to-top insertion sequence, starting from Group 3 (bottom cells) up to Group 1 (top cells).

Result: Upon completion of the connection, smoke and a visible burn occurred near resistor R1_1 (10 ohm). We immediately cut off the power supply to prevent further damage and inspected the board.

Post-Mortem & Damage Analysis:

VBAT_1 to GND_1 Short Circuit: Electrical testing revealed a dead short between VBAT_1 and GND_1. Since this power line feeds directly into the balancing IC, we suspected internal silicon failure.
Resistor R1_1: The 10 ohm resistor was found to be blown open (open-circuit).
CT & CB Pins: Inspected both CT and CB pins; there was no physical or electrical damage detected on these pins.
Balancing Resistors: Inspected all external cell-balancing resistors; all remain intact and undamaged.
IC Root Cause Verification: We desoldered the balancing IC from the PCB to isolate the issue. Testing the unmounted IC confirmed a permanent internal short circuit between the VBAT and GND pins.

Questions for NXP Support:

Given that the configuration works flawlessly when Group 1 is powered up individually, what could trigger an internal VBAT-to-GND breakdown inside the balancing IC when all three groups are plugged in sequentially (from bottom to top)?
Could the termination method of shorting the unused pins (CB15-18 to CB14, and CT15-18 to CT14) induce unexpected transient states or latch-up conditions during multi-chip daisy-chain hot-plugging?
What specific hot-plug protection, TVS adjustments, or power-up sequencing constraints do we need to implement to mitigate this failure mode?

Please help us analyze and recommend ways to resolve this issue