Power ManagementのトピックAsk for FS26 drawing source document

Ask for FS26 drawing source document

ChandlerBing — Sun, 05 Jul 2026 11:34:36 GMT

Dear Support Team,

I’m engaged in software development based on FS26 SBC. The attached figure is quoted in our software development materials, yet I failed to locate its original official document.

Please help confirm which NXP FS26 document (datasheet / AN / safety manual / design guide) includes this diagram, and provide the corresponding document ID as well as figure chapter information.

Thank you very much for your assistance.

Regards,

Re: Ask for FS26 drawing source document

TomasVaverka — Sun, 05 Jul 2026 18:20:51 GMT

Dear Lai,

I suppose that the document snippet you provided does not actually come from our FS26 documents. Instead it originates from the datasheet for the FS6500/FS4500 SBC family.

Since you are developing software for the newer FS26 SBC family, you should look into the FS26 software quick start guide (AN14492), FS26 implementation and behaviors (AN12995) or the full FS26 datasheet instead.

BRs, Tomas

Re: Ask for FS26 drawing source document

ChandlerBing — Mon, 06 Jul 2026 09:31:08 GMT

Dear Tomas,
Thank you very much for your prompt clarification and guidance!
Besides, I have another debug issue to consult you.
Our system uses FS26 to supply FC7300 MCU. After FS26 enters FS_STATES_NORMAL_FS operational state, connecting J-Link will cause the RST pin to be pulled low multiple times consecutively, resulting in debugger connection failure.
In normal running mode with regular watchdog refresh, the reset issue never occurs.
Could you help analyze the root cause of this multi-reset phenomenon and share corresponding register configuration or hardware solutions?
Thanks again for your support.
Best regards,
Lai

Re: Ask for FS26 drawing source document

HajoV — Mon, 13 Jul 2026 15:20:15 GMT

Hello,

I assume Jlink means connecting to JTAG?

If You have repeating resets in a usually running system when connecting JTAG it sounds like there were some watchdog errors.

Not really a surprise when an external debugger is in the game, which is interfering in CPU operation.

We are using FS4500 and to my memory we always activate debug mode prior to using JTAG, because we do not have a CPU-SW snippet running that is acting the Watchdog during JTAG interference.

To my humble understanding this is what the debug mode was made for.