topic Re: AN1902 QFN Footprint Guidelines in Power Management

AN1902 QFN Footprint Guidelines

JimBKHS — Fri, 17 Oct 2025 16:01:23 GMT

I'm reviewing AN1902 on QFN and SON package assembly guidelines and had a specific question about thermal via recommendations. I'm specifically reviewing what to do with thermal vias placed within the exposed pads of these package footprints.

I always thought it was best to UNTENT thermal vias placed within the exposed die pad on the opposite solder mask side, as tenting them would realistically trap a void of air within the via itself and lead to PCB damage during thermal cycles of the assembly. However, page 16 of the app note recommends this:

"If the copper plating does not plug the vias, then the thermal vias can be “tented” with
solder mask on the top surface of the PCB to avoid solder wicking inside the via during
assembly. The solder mask diameter should be at least 0.10 mm larger than the via
diameter."

So it sounds like the primary goal is to tent the back side of the thermal vias to limit solder reflow into these vias, but with the vias tented won't a void of air (albeit small) be trapped in the via itself? Can't this cause other issues?

Re: AN1902 QFN Footprint Guidelines

RafaR — Fri, 24 Oct 2025 00:15:20 GMT

Hello JimBKHS

Good day!

The recommendation in AN1902 to tent thermal vias on the top side (component side) is primarily to prevent solder wicking during reflow.

Your concern about trapped air in shielded vias is valid. However, modern solder mask materials and via shielding techniques are designed to minimize this risk. The void is typically very small and unlikely to cause damage unless the via is large or the board is under extreme thermal stress.

Usually, each company that manufactures PCB already has its own methods and practices to minimize this risk.

As extra note:

If possible, use via fill and cap plating (IPC-4761 Type VII) to completely seal the via. This avoids both solder wicking and air entrapment.

I hope this information has helped you, please let me know if you need help with anything else.

Have a great day and best of luck.

Re: AN1902 QFN Footprint Guidelines

JimBKHS — Fri, 24 Oct 2025 14:09:22 GMT

Thanks @RafaR I think I was misunderstanding the via tenting, and thought the app note was suggesting tenting on the OPPOSITE of component side, which would definitely trap air voids.

So it looks like the overall thermal via recommendation from this app note is (obviously component, supplier recommendation and process dependent)

Use a 1.2mm grid array of vias
Which are sized 0.3 to 0.33mm in hole diameter
Plated to 1oz copper
And optionally tented on the component side with mask at a diameter +0.1mm larger than the hole size

Correct?

Re: AN1902 QFN Footprint Guidelines

RafaR — Fri, 24 Oct 2025 15:36:05 GMT

Hello JimBKHS

Good day!

Yes, your analysis sounds good. As you mentioned, it may vary depending on the component, process used, etc.

But I think you've captured the most important points to consider.

Have a great day and best of luck.