topic Re: PCA9451A PWRON_STAT register in Power Management

PCA9451A PWRON_STAT register

wooosaiiii — Tue, 02 Sep 2025 08:54:28 GMT

Hi,

We are using i.MX93 SoM with PCA9451A PMIC.

We are reading the PMIC's PWRON_STAT (0x05) register in U-Boot.

In case of a reset command or watchdog timeout, the appropriate bits are set!

e.g. U-Boot reset (i2c command sent to PMIC to reset):

bit 5 -> SW_RST

e.g. U-Boot watchdog timeout (simulate with loop 0 0 command):

bit 6 -> WDOG

However, when unplugging/plugging in power, two bits are set in this register.

Read register value 0x90 -> bit7 and bit4

bit 7 ... PWRON (expected)

bit 4 ... PMIC_RST (not expected)

Is this expected?

Are we supposed to read all bits? How to choose then if 2 bits set which reset reason was performed?

Re: PCA9451A PWRON_STAT register

TomasVaverka — Tue, 02 Sep 2025 10:25:59 GMT

Hi Primoz,

Yes, this is expected. The PCA9451A can and does set multiple bits in PWRON_STAT when more than one reset/event happened and the bits are latched until read. Perhaps you can apply a priority rule in software. Example:

If PWRON set → treat as power-on (power-cycle) boot.
else if WDOG set → treat as watchdog reset.
else if SW_RST set → treat as software reset.
else if PMIC_RST set → treat as PMIC pin reset.

BRs, Tomas

Re: PCA9451A PWRON_STAT register

wooosaiiii — Tue, 02 Sep 2025 10:31:14 GMT

Hi @TomasVaverka , Thanks for your input.

Can you say bits are already arranged by the order of priority?

BIT7 -> top priority

BIT4 -> lowest priority

I want as generic an implementation as possible.