<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Is VREFDDR disabled by default? in Power Management</title>
    <link>https://community.nxp.com/t5/Power-Management/Is-VREFDDR-disabled-by-default/m-p/2051145#M4148</link>
    <description>&lt;P&gt;I plan to use&amp;nbsp;MMPF0100 F0 mode. (Part&amp;nbsp;MMPF0100F0ANES)&lt;/P&gt;&lt;P&gt;I plan to use the&amp;nbsp;VREFDDR voltage follower feature for DDR3(L) instead of using resistors as a voltage divider for DDR_VREF&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The datasheet for PF0100's&amp;nbsp;VREFDDCRTL register on page 26, it says:&lt;/P&gt;&lt;P&gt;"Enable or disables VREFDDR output voltage • 0 = VREFDDR Disabled • 1 = VREFDDR Enabled "&lt;/P&gt;&lt;P&gt;And under the "Default" column the setting is 0x0&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;However the Device Start-up Configuration page (18) shows both the 'Default configuration' and 'F0' modes having the VREFDDR_SEQ set to '3' with no mention of it being enabled or disabled.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Q1: Is the&amp;nbsp;VREFDDR output disabled for modes 'default' and 'F0' or will it come up at sequence 3?&lt;/P&gt;&lt;P&gt;Q2: If it is disabled, is the intention for the controlling device (U-Boot) to start up using sram alone, contain PFUZE100 drivers and devicetree and enable&amp;nbsp;VREFDDR?&lt;/P&gt;&lt;P&gt;Q3: If it is disabled, which other part number of PF0100 has it enabled by default?&lt;/P&gt;</description>
    <pubDate>Tue, 25 Feb 2025 22:52:51 GMT</pubDate>
    <dc:creator>ghazanhaider</dc:creator>
    <dc:date>2025-02-25T22:52:51Z</dc:date>
    <item>
      <title>Is VREFDDR disabled by default?</title>
      <link>https://community.nxp.com/t5/Power-Management/Is-VREFDDR-disabled-by-default/m-p/2051145#M4148</link>
      <description>&lt;P&gt;I plan to use&amp;nbsp;MMPF0100 F0 mode. (Part&amp;nbsp;MMPF0100F0ANES)&lt;/P&gt;&lt;P&gt;I plan to use the&amp;nbsp;VREFDDR voltage follower feature for DDR3(L) instead of using resistors as a voltage divider for DDR_VREF&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The datasheet for PF0100's&amp;nbsp;VREFDDCRTL register on page 26, it says:&lt;/P&gt;&lt;P&gt;"Enable or disables VREFDDR output voltage • 0 = VREFDDR Disabled • 1 = VREFDDR Enabled "&lt;/P&gt;&lt;P&gt;And under the "Default" column the setting is 0x0&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;However the Device Start-up Configuration page (18) shows both the 'Default configuration' and 'F0' modes having the VREFDDR_SEQ set to '3' with no mention of it being enabled or disabled.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Q1: Is the&amp;nbsp;VREFDDR output disabled for modes 'default' and 'F0' or will it come up at sequence 3?&lt;/P&gt;&lt;P&gt;Q2: If it is disabled, is the intention for the controlling device (U-Boot) to start up using sram alone, contain PFUZE100 drivers and devicetree and enable&amp;nbsp;VREFDDR?&lt;/P&gt;&lt;P&gt;Q3: If it is disabled, which other part number of PF0100 has it enabled by default?&lt;/P&gt;</description>
      <pubDate>Tue, 25 Feb 2025 22:52:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Power-Management/Is-VREFDDR-disabled-by-default/m-p/2051145#M4148</guid>
      <dc:creator>ghazanhaider</dc:creator>
      <dc:date>2025-02-25T22:52:51Z</dc:date>
    </item>
    <item>
      <title>Re: Is VREFDDR disabled by default?</title>
      <link>https://community.nxp.com/t5/Power-Management/Is-VREFDDR-disabled-by-default/m-p/2051339#M4149</link>
      <description>&lt;P&gt;HI&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Q1: Is the&amp;nbsp;VREFDDR output disabled for modes 'default' and 'F0' or will it come up at sequence 3?&lt;/P&gt;
&lt;P&gt;--Following F0&lt;/P&gt;
&lt;P&gt;Q2: If it is disabled, is the intention for the controlling device (U-Boot) to start up using sram alone, contain PFUZE100 drivers and devicetree and enable&amp;nbsp;VREFDDR?&lt;/P&gt;
&lt;P&gt;--xxx&lt;/P&gt;
&lt;P&gt;Q3: If it is disabled, which other part number of PF0100 has it enabled by default?&lt;/P&gt;
&lt;P&gt;--xxx&lt;/P&gt;</description>
      <pubDate>Wed, 26 Feb 2025 05:50:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Power-Management/Is-VREFDDR-disabled-by-default/m-p/2051339#M4149</guid>
      <dc:creator>guoweisun</dc:creator>
      <dc:date>2025-02-26T05:50:43Z</dc:date>
    </item>
    <item>
      <title>Re: Is VREFDDR disabled by default?</title>
      <link>https://community.nxp.com/t5/Power-Management/Is-VREFDDR-disabled-by-default/m-p/2052285#M4150</link>
      <description>Please clarify:&lt;BR /&gt;"Following F0"&lt;BR /&gt;Does this mean VREFDDR is enabled in F0 parts?</description>
      <pubDate>Wed, 26 Feb 2025 22:04:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Power-Management/Is-VREFDDR-disabled-by-default/m-p/2052285#M4150</guid>
      <dc:creator>ghazanhaider</dc:creator>
      <dc:date>2025-02-26T22:04:25Z</dc:date>
    </item>
  </channel>
</rss>

