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    <title>topic Re: UJA1169ATK/F V1 undervoltage reset in Power Management</title>
    <link>https://community.nxp.com/t5/Power-Management/UJA1169ATK-F-V1-undervoltage-reset/m-p/1739866#M3016</link>
    <description>&lt;P&gt;HI.guoweisun&lt;/P&gt;&lt;P&gt;I would like to ask a technical question about the UJA1169A, and since I didn't find a way how to post a new thread, this is the only way I can ask you.&lt;/P&gt;&lt;P&gt;As shown in the figure below, Vth(sw)r is the threshold for the rising edge from a low level to a high level, and Vth(sw)f is the threshold for the falling edge from a high level to a low level, why is there an intersection between these two thresholds?2.8V is contained within 3.75VHow is this understood?&lt;/P&gt;&lt;P&gt;For the UJA1169A, can the WAKE pin be internally configured with a pull-up or pull-down circuit? If the input signal is active low, must the WAKE pin have a resistor pull-up circuit?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Mon, 16 Oct 2023 01:21:37 GMT</pubDate>
    <dc:creator>JLDN0101</dc:creator>
    <dc:date>2023-10-16T01:21:37Z</dc:date>
    <item>
      <title>UJA1169ATK/F V1 undervoltage reset</title>
      <link>https://community.nxp.com/t5/Power-Management/UJA1169ATK-F-V1-undervoltage-reset/m-p/1724324#M2961</link>
      <description>&lt;P&gt;Hello, we use battery to supply VBAT(6.66V~7V),&amp;nbsp;V1RTSUC is 80% and&amp;nbsp;V1RTC is 90%, then SBC will reset, and RSS in Main status register(03h) will return 10011(V1 undervoltage).&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="V1 undervoltage,VBAT is OK" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/241315iFF7045292B8DC41D/image-size/medium?v=v2&amp;amp;px=400" role="button" title="1.jpg" alt="V1 undervoltage,VBAT is OK" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;V1 undervoltage,VBAT is OK&lt;/span&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;Increase the voltage on VBAT to 8V, the temperature will influence V1: UJA1169 will be OK below 65℃；while it will reset due to V1 undervoltage above 65℃.&lt;/P&gt;&lt;P&gt;When VBAT is 13V, the SBC is OK.&lt;/P&gt;&lt;P&gt;So, why VBAT and temperature will result in V1 undervoltage?&lt;/P&gt;</description>
      <pubDate>Mon, 18 Sep 2023 02:40:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Power-Management/UJA1169ATK-F-V1-undervoltage-reset/m-p/1724324#M2961</guid>
      <dc:creator>larry_he</dc:creator>
      <dc:date>2023-09-18T02:40:40Z</dc:date>
    </item>
    <item>
      <title>Re: UJA1169ATK/F V1 undervoltage reset</title>
      <link>https://community.nxp.com/t5/Power-Management/UJA1169ATK-F-V1-undervoltage-reset/m-p/1724441#M2962</link>
      <description>&lt;P&gt;V1 is the internal LDO of UJA1169, so the MOSFET Rdson will increase when temperature rise.&lt;/P&gt;
&lt;P&gt;So you can get the temperature affect the V1 of UJA1169.&lt;/P&gt;</description>
      <pubDate>Mon, 18 Sep 2023 06:04:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Power-Management/UJA1169ATK-F-V1-undervoltage-reset/m-p/1724441#M2962</guid>
      <dc:creator>guoweisun</dc:creator>
      <dc:date>2023-09-18T06:04:51Z</dc:date>
    </item>
    <item>
      <title>Re: UJA1169ATK/F V1 undervoltage reset</title>
      <link>https://community.nxp.com/t5/Power-Management/UJA1169ATK-F-V1-undervoltage-reset/m-p/1724497#M2963</link>
      <description>&lt;P&gt;But will 65℃ make undervoltage happen? And when VBAT is 13V, 65℃ will not result in V1 undervoltage.&lt;/P&gt;</description>
      <pubDate>Mon, 18 Sep 2023 06:43:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Power-Management/UJA1169ATK-F-V1-undervoltage-reset/m-p/1724497#M2963</guid>
      <dc:creator>larry_he</dc:creator>
      <dc:date>2023-09-18T06:43:41Z</dc:date>
    </item>
    <item>
      <title>Re: UJA1169ATK/F V1 undervoltage reset</title>
      <link>https://community.nxp.com/t5/Power-Management/UJA1169ATK-F-V1-undervoltage-reset/m-p/1724553#M2965</link>
      <description>&lt;P&gt;For the LDO,VOUT= Vin - Vdrop, Vdrop will be affected by the Rdson of internal MOSFET, when the VIN and VOUT are similar value, the UV condition will easily happen.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 18 Sep 2023 07:56:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Power-Management/UJA1169ATK-F-V1-undervoltage-reset/m-p/1724553#M2965</guid>
      <dc:creator>guoweisun</dc:creator>
      <dc:date>2023-09-18T07:56:49Z</dc:date>
    </item>
    <item>
      <title>Re: UJA1169ATK/F V1 undervoltage reset</title>
      <link>https://community.nxp.com/t5/Power-Management/UJA1169ATK-F-V1-undervoltage-reset/m-p/1724599#M2966</link>
      <description>&lt;P&gt;Is&amp;nbsp;&lt;SPAN&gt;Rdson&amp;nbsp;RON(BAT-V1) (Can VBAT be 2.8V?)? Or do you have the value of Rdson?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="2.png" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/241399i83E0B24BD993EE2D/image-size/large?v=v2&amp;amp;px=999" role="button" title="2.png" alt="2.png" /&gt;&lt;/span&gt;&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Mon, 18 Sep 2023 08:59:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Power-Management/UJA1169ATK-F-V1-undervoltage-reset/m-p/1724599#M2966</guid>
      <dc:creator>larry_he</dc:creator>
      <dc:date>2023-09-18T08:59:44Z</dc:date>
    </item>
    <item>
      <title>Re: UJA1169ATK/F V1 undervoltage reset</title>
      <link>https://community.nxp.com/t5/Power-Management/UJA1169ATK-F-V1-undervoltage-reset/m-p/1727496#M2972</link>
      <description>&lt;P&gt;是这个参数，我从你抓的波形上看V1输出往下掉的很厉害，可能是瞬态电流太大导致的。&lt;/P&gt;
&lt;P&gt;你可以问问客户他这个测试条件瞬态电流能到多少？是不是超出了规格？正常值带载能力也就是200mA左右！&lt;/P&gt;</description>
      <pubDate>Fri, 22 Sep 2023 00:15:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Power-Management/UJA1169ATK-F-V1-undervoltage-reset/m-p/1727496#M2972</guid>
      <dc:creator>guoweisun</dc:creator>
      <dc:date>2023-09-22T00:15:05Z</dc:date>
    </item>
    <item>
      <title>Re: UJA1169ATK/F V1 undervoltage reset</title>
      <link>https://community.nxp.com/t5/Power-Management/UJA1169ATK-F-V1-undervoltage-reset/m-p/1739377#M3013</link>
      <description>&lt;P&gt;HI.guoweisun&lt;/P&gt;&lt;P&gt;I would like to ask a technical question about the UJA1169A, and since I didn't find a way how to post a new thread, this is the only way I can ask you.&lt;/P&gt;&lt;P&gt;As shown in the figure below, Vth(sw)r is the threshold for the rising edge from a low level to a high level, and Vth(sw)f is the threshold for the falling edge from a high level to a low level, why is there an intersection between these two thresholds?2.8V is contained within 3.75VHow is this understood?&lt;/P&gt;&lt;P&gt;For the UJA1169A, can the WAKE pin be internally configured with a pull-up or pull-down circuit? If the input signal is active low, must the WAKE pin have a resistor pull-up circuit?&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="JLDN0101_0-1697188461125.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/244996i0FCC813D96027835/image-size/medium?v=v2&amp;amp;px=400" role="button" title="JLDN0101_0-1697188461125.png" alt="JLDN0101_0-1697188461125.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 13 Oct 2023 09:20:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Power-Management/UJA1169ATK-F-V1-undervoltage-reset/m-p/1739377#M3013</guid>
      <dc:creator>JLDN0101</dc:creator>
      <dc:date>2023-10-13T09:20:50Z</dc:date>
    </item>
    <item>
      <title>Re: UJA1169ATK/F V1 undervoltage reset</title>
      <link>https://community.nxp.com/t5/Power-Management/UJA1169ATK-F-V1-undervoltage-reset/m-p/1739402#M3014</link>
      <description>&lt;P&gt;如果是其他的topic，我建议您直接提交ticket下面的链接需要您的邮箱注册，我们会一对一的提供支持，回复的内容只有您自己看得到：&lt;/P&gt;
&lt;P&gt;&lt;A href="https://support.nxp.com/s/?language=en_US" target="_blank"&gt;Home (nxp.com)&lt;/A&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 13 Oct 2023 09:27:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Power-Management/UJA1169ATK-F-V1-undervoltage-reset/m-p/1739402#M3014</guid>
      <dc:creator>guoweisun</dc:creator>
      <dc:date>2023-10-13T09:27:29Z</dc:date>
    </item>
    <item>
      <title>Re: UJA1169ATK/F V1 undervoltage reset</title>
      <link>https://community.nxp.com/t5/Power-Management/UJA1169ATK-F-V1-undervoltage-reset/m-p/1739866#M3016</link>
      <description>&lt;P&gt;HI.guoweisun&lt;/P&gt;&lt;P&gt;I would like to ask a technical question about the UJA1169A, and since I didn't find a way how to post a new thread, this is the only way I can ask you.&lt;/P&gt;&lt;P&gt;As shown in the figure below, Vth(sw)r is the threshold for the rising edge from a low level to a high level, and Vth(sw)f is the threshold for the falling edge from a high level to a low level, why is there an intersection between these two thresholds?2.8V is contained within 3.75VHow is this understood?&lt;/P&gt;&lt;P&gt;For the UJA1169A, can the WAKE pin be internally configured with a pull-up or pull-down circuit? If the input signal is active low, must the WAKE pin have a resistor pull-up circuit?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 16 Oct 2023 01:21:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Power-Management/UJA1169ATK-F-V1-undervoltage-reset/m-p/1739866#M3016</guid>
      <dc:creator>JLDN0101</dc:creator>
      <dc:date>2023-10-16T01:21:37Z</dc:date>
    </item>
    <item>
      <title>Re: UJA1169ATK/F V1 undervoltage reset</title>
      <link>https://community.nxp.com/t5/Power-Management/UJA1169ATK-F-V1-undervoltage-reset/m-p/1740296#M3021</link>
      <description>&lt;P&gt;这个客户提交了一个ticket今天已经帮他回复了&lt;/P&gt;</description>
      <pubDate>Mon, 16 Oct 2023 09:32:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Power-Management/UJA1169ATK-F-V1-undervoltage-reset/m-p/1740296#M3021</guid>
      <dc:creator>guoweisun</dc:creator>
      <dc:date>2023-10-16T09:32:43Z</dc:date>
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