https://community.nxp.com/t5/Power-Management/KITPF8200FRDPGM-error/m-p/1676441#M2761 <P>i use KITPF8200FRDPGM and MC33PF8200</P><P>TBB Mode is Possibe But OTP Mode is not possible</P><P>here is my script&nbsp;</P><P>OTP:</P><P>&nbsp;</P><P>SET_DPIN:PF8200:PWRON:low<BR />SET_DPIN:PF8200:WDI:low<BR />SET_DPIN:PF8200:TBBEN:high<BR />SET_DPIN:PF8200:USBEN:high<BR />SET_DPIN:PF8200:BSTEN:high<BR />SET_DPIN:PF8200:VDDOTPEN:high<BR />SET_REG:PF8200:OTP_MIRROR:OTP_FSOB_SELECT:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_I2C:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_CTRL1:0x0A<BR />SET_REG:PF8200:OTP_MIRROR:OTP_CTRL2:0x41<BR />SET_REG:PF8200:OTP_MIRROR:OTP_CTRL3:0x41<BR />SET_REG:PF8200:OTP_MIRROR:OTP_FREQ_CTRL:0x80<BR />SET_REG:PF8200:OTP_MIRROR:OTP_COINCELL_CTRL:0x0B<BR />SET_REG:PF8200:OTP_MIRROR:OTP_PWRON:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_WD_CONFIG:0x10<BR />SET_REG:PF8200:OTP_MIRROR:OTP_WD_EXPIRE:0x07<BR />SET_REG:PF8200:OTP_MIRROR:OTP_WD_COUNTER:0xAF<BR />SET_REG:PF8200:OTP_MIRROR:OTP_FAULT_COUNTER:0xF0<BR />SET_REG:PF8200:OTP_MIRROR:OTP_FAULT_TIMERS:0x7F<BR />SET_REG:PF8200:OTP_MIRROR:OTP_PWRDN_DLY1:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_PWRDN_DLY2:0x81<BR />SET_REG:PF8200:OTP_MIRROR:OTP_PWRUP_CTRL:0x02<BR />SET_REG:PF8200:OTP_MIRROR:OTP_RESETBMCU_PWRUP:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_PGOOD_PWRUP:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW1_VOLT:0x20<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW1_PWRUP:0x15<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW1_CONFIG1:0x53<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW1_CONFIG2:0x09<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW2_VOLT:0x70<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW2_PWRUP:0x15<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW2_CONFIG1:0x53<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW2_CONFIG2:0x29<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW3_VOLT:0x60<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW3_PWRUP:0x3D<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW3_CONFIG1:0x53<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW3_CONFIG2:0x3B<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW4_VOLT:0xB1<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW4_PWRUP:0x47<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW4_CONFIG1:0x53<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW4_CONFIG2:0x2B<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW5_VOLT:0xB0<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW5_PWRUP:0x51<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW5_CONFIG1:0x53<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW5_CONFIG2:0x33<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW6_VOLT:0x38<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW6_PWRUP:0x51<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW6_CONFIG1:0x53<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW6_CONFIG2:0x13<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW7_VOLT:0x15<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW7_PWRUP:0x47<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW7_CONFIG1:0x53<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW7_CONFIG2:0x03<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO1_VOLT:0x52<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO1_PWRUP:0x5B<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO1_CONFIG:0x06<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO2_VOLT:0x50<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO2_PWRUP:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO2_CONFIG:0x12<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO3_VOLT:0x52<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO3_PWRUP:0x65<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO3_CONFIG:0x06<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO4_VOLT:0x52<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO4_PWRUP:0x6F<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO4_CONFIG:0x06<BR />SET_REG:PF8200:OTP_MIRROR:OTP_VSNVS_CONFIG:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_OV_BYPASS1:0x7F<BR />SET_REG:PF8200:OTP_MIRROR:OTP_OV_BYPASS2:0x0F<BR />SET_REG:PF8200:OTP_MIRROR:OTP_UV_BYPASS1:0x7F<BR />SET_REG:PF8200:OTP_MIRROR:OTP_UV_BYPASS2:0x0F<BR />SET_REG:PF8200:OTP_MIRROR:OTP_ILIM_BYPASS1:0x7F<BR />SET_REG:PF8200:OTP_MIRROR:OTP_ILIM_BYPASS2:0x0F<BR />SET_REG:PF8200:OTP_MIRROR:OTP_PROG_IDH:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_PROG_IDL:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_DEBUG1:0x01<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW_COMP1:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW_COMP2:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW_COMP3:0x00</P><P>// CONFIGURE OTP CONTROLLER<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0x80<BR />SET_REG:PF8200:OTP_PAGE2:FADDR_START:0x00<BR />SET_REG:PF8200:OTP_PAGE2:FDATA:0xAC<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0xA9<BR />SET_REG:PF8200:OTP_PAGE2:FADDR_START:0x02<BR />SET_REG:PF8200:OTP_PAGE2:FDATA:0xDC<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0xA9<BR />SET_REG:PF8200:OTP_PAGE2:FADDR_START:0x08<BR />SET_REG:PF8200:OTP_PAGE2:FDATA:0x38<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0xA9<BR />SET_REG:PF8200:OTP_PAGE2:FADDR_START:0x09<BR />SET_REG:PF8200:OTP_PAGE2:FDATA:0xDC<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0xA9<BR />SET_REG:PF8200:OTP_PAGE2:FADDR_START:0x0C<BR />SET_REG:PF8200:OTP_PAGE2:FDATA:0xD2<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0xA9</P><P>SET_REG:PF8200:OTP_PAGE2:MAX_PGM_TRIES:0x08<BR />SET_REG:PF8200:OTP_PAGE2:MRR_SVDR_IN:0x13<BR />SET_REG:PF8200:OTP_PAGE2:MR_TEST_H:0x00<BR />SET_REG:PF8200:OTP_PAGE2:MR_TEST_L:0x02<BR />SET_REG:PF8200:OTP_PAGE2:MREF_TEST_H:0x00<BR />SET_REG:PF8200:OTP_PAGE2:MREF_TEST_L:0x00<BR />SET_REG:PF8200:OTP_PAGE2:PULSE_DUR_1:0xBB<BR />SET_REG:PF8200:OTP_PAGE2:PULSE_DUR_2:0x08<BR />SET_REG:PF8200:OTP_PAGE2:FADDR_START:0x00<BR />SET_REG:PF8200:OTP_PAGE2:FADDR_STOP:0x48</P><P>// SET CRC VALUES<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0xA5<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0xA4<BR />GET_REG:PF8200:OTP_MIRROR:OTP_S0_CRC_LSB<BR />GET_REG:PF8200:OTP_MIRROR:OTP_S0_CRC_MSB<BR />GET_REG:PF8200:OTP_PAGE2:SECT_STATUS</P><P>// START FUSE PROGRAMMING<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0x96<BR />GET_REG:PF8200:OTP_PAGE2:FSTATUS<BR />GET_REG:PF8200:OTP_PAGE2:FSTATUS<BR />GET_REG:PF8200:OTP_PAGE2:FSTATUS<BR />GET_REG:PF8200:OTP_PAGE2:FSTATUS<BR />GET_REG:PF8200:OTP_PAGE2:FSTATUS<BR />GET_REG:PF8200:OTP_PAGE2:FSTATUS<BR />GET_REG:PF8200:OTP_PAGE2:FSTATUS<BR />GET_REG:PF8200:OTP_PAGE2:FSTATUS</P><P>// BURN BOOT ENABLE AND WRITE PROTECT BITS<BR />SET_REG:PF8200:OTP_PAGE2:FADDR_STOP:0xFF<BR />SET_REG:PF8200:OTP_PAGE2:FADDR_START:0xFE<BR />SET_REG:PF8200:OTP_PAGE2:FDATA:0xAA<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0x87<BR />GET_REG:PF8200:OTP_PAGE2:FSTATUS<BR />GET_REG:PF8200:OTP_PAGE2:FSTATUS<BR />SET_REG:PF8200:OTP_PAGE2:FADDR_START:0xFF<BR />SET_REG:PF8200:OTP_PAGE2:FDATA:0x55<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0x87<BR />GET_REG:PF8200:OTP_PAGE2:FSTATUS<BR />GET_REG:PF8200:OTP_PAGE2:FSTATUS<BR />SET_REG:PF8200:OTP_PAGE2:FADDR_START:0xFC<BR />SET_REG:PF8200:OTP_PAGE2:FDATA:0xAA<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0x87<BR />GET_REG:PF8200:OTP_PAGE2:FSTATUS<BR />GET_REG:PF8200:OTP_PAGE2:FSTATUS<BR />SET_REG:PF8200:OTP_PAGE2:FADDR_START:0xFD<BR />SET_REG:PF8200:OTP_PAGE2:FDATA:0x55<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0x87<BR />GET_REG:PF8200:OTP_PAGE2:FSTATUS<BR />GET_REG:PF8200:OTP_PAGE2:FSTATUS<BR />GET_REG:PF8200:OTP_PAGE2:SECT_STATUS</P><P>SET_DPIN:PF8200:USBEN:low<BR />SET_DPIN:PF8200:BSTEN:low<BR />SET_DPIN:PF8200:VDDOTPEN:low</P><P>//Verify Mirror Registers = Fuse Value<BR />GET_REG:PF8200:functional:DEVICE_ID<BR />SET_REG:PF8200:OTP_PAGE2:FADDR_START:0x00<BR />SET_REG:PF8200:OTP_PAGE2:FADDR_STOP:0x48<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0xAB<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0xA0<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0xA1<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0xA4<BR />GET_REG:PF8200:OTP_MIRROR:OTP_S0_CRC_LSB<BR />GET_REG:PF8200:OTP_MIRROR:OTP_S0_CRC_MSB<BR />GET_REG:PF8200:OTP_PAGE2:SECT_STATUS<BR />GET_REG:PF8200:OTP_PAGE2:FSTATUS</P><P>//If SECT_STATUS = 0x3F &amp; FSTATUS = 0x00 part is programmed correctly.<BR />//Verify CRC_LSB and CRC_MSB match the values in section "SET CRC VALUES" .<BR />SET_DPIN:PF8200:TBBEN:low</P><P>&nbsp;</P><P>TBB:</P><P>SET_DPIN:PF8200:PWRON:low<BR />SET_DPIN:PF8200:WDI:low<BR />SET_DPIN:PF8200:TBBEN:high<BR />SET_REG:PF8200:OTP_MIRROR:OTP_FSOB_SELECT:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_I2C:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_CTRL1:0x0A<BR />SET_REG:PF8200:OTP_MIRROR:OTP_CTRL2:0x41<BR />SET_REG:PF8200:OTP_MIRROR:OTP_CTRL3:0x41<BR />SET_REG:PF8200:OTP_MIRROR:OTP_FREQ_CTRL:0x80<BR />SET_REG:PF8200:OTP_MIRROR:OTP_COINCELL_CTRL:0x0B<BR />SET_REG:PF8200:OTP_MIRROR:OTP_PWRON:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_WD_CONFIG:0x10<BR />SET_REG:PF8200:OTP_MIRROR:OTP_WD_EXPIRE:0x07<BR />SET_REG:PF8200:OTP_MIRROR:OTP_WD_COUNTER:0xAF<BR />SET_REG:PF8200:OTP_MIRROR:OTP_FAULT_COUNTER:0xF0<BR />SET_REG:PF8200:OTP_MIRROR:OTP_FAULT_TIMERS:0x7F<BR />SET_REG:PF8200:OTP_MIRROR:OTP_PWRDN_DLY1:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_PWRDN_DLY2:0x81<BR />SET_REG:PF8200:OTP_MIRROR:OTP_PWRUP_CTRL:0x02<BR />SET_REG:PF8200:OTP_MIRROR:OTP_RESETBMCU_PWRUP:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_PGOOD_PWRUP:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW1_VOLT:0x20<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW1_PWRUP:0x15<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW1_CONFIG1:0x53<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW1_CONFIG2:0x09<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW2_VOLT:0x70<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW2_PWRUP:0x15<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW2_CONFIG1:0x53<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW2_CONFIG2:0x29<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW3_VOLT:0x60<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW3_PWRUP:0x3D<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW3_CONFIG1:0x53<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW3_CONFIG2:0x3B<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW4_VOLT:0xB1<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW4_PWRUP:0x47<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW4_CONFIG1:0x53<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW4_CONFIG2:0x2B<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW5_VOLT:0xB0<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW5_PWRUP:0x51<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW5_CONFIG1:0x53<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW5_CONFIG2:0x33<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW6_VOLT:0x38<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW6_PWRUP:0x51<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW6_CONFIG1:0x53<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW6_CONFIG2:0x13<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW7_VOLT:0x15<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW7_PWRUP:0x47<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW7_CONFIG1:0x53<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW7_CONFIG2:0x03<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO1_VOLT:0x52<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO1_PWRUP:0x5B<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO1_CONFIG:0x06<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO2_VOLT:0x50<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO2_PWRUP:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO2_CONFIG:0x12<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO3_VOLT:0x52<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO3_PWRUP:0x65<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO3_CONFIG:0x06<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO4_VOLT:0x52<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO4_PWRUP:0x6F<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO4_CONFIG:0x06<BR />SET_REG:PF8200:OTP_MIRROR:OTP_VSNVS_CONFIG:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_OV_BYPASS1:0x7F<BR />SET_REG:PF8200:OTP_MIRROR:OTP_OV_BYPASS2:0x0F<BR />SET_REG:PF8200:OTP_MIRROR:OTP_UV_BYPASS1:0x7F<BR />SET_REG:PF8200:OTP_MIRROR:OTP_UV_BYPASS2:0x0F<BR />SET_REG:PF8200:OTP_MIRROR:OTP_ILIM_BYPASS1:0x7F<BR />SET_REG:PF8200:OTP_MIRROR:OTP_ILIM_BYPASS2:0x0F<BR />SET_REG:PF8200:OTP_MIRROR:OTP_PROG_IDH:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_PROG_IDL:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_DEBUG1:0x01<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW_COMP1:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW_COMP2:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW_COMP3:0x00<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0xA5<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0xA4<BR />SET_REG:PF8200:functional:TEST_FLAGS:0x07<BR />SET_DPIN:PF8200:TBBEN:low<BR />SET_DPIN:PF8200:PWRON:high</P><P>&nbsp;</P><P>OTP Result:</P><P>OK: set PWRON digital pin = LOW<BR />OK: set WDI digital pin = LOW<BR />OK: set TBBEN digital pin = HIGH<BR />OK: set USBEN digital pin = HIGH<BR />OK: set BSTEN digital pin = HIGH<BR />OK: set VDDOTPEN digital pin = HIGH<BR />OK: write reg. OTP_FSOB_SELECT = 0x00<BR />OK: write reg. OTP_I2C = 0x00<BR />OK: write reg. OTP_CTRL1 = 0x0a<BR />OK: write reg. OTP_CTRL2 = 0x41<BR />OK: write reg. OTP_CTRL3 = 0x41<BR />OK: write reg. OTP_FREQ_CTRL = 0x80<BR />OK: write reg. OTP_COINCELL_CTRL = 0x0b<BR />OK: write reg. OTP_PWRON = 0x00<BR />OK: write reg. OTP_WD_CONFIG = 0x10<BR />OK: write reg. OTP_WD_EXPIRE = 0x07<BR />OK: write reg. OTP_WD_COUNTER = 0xaf<BR />OK: write reg. OTP_FAULT_COUNTER = 0xf0<BR />OK: write reg. OTP_FAULT_TIMERS = 0x7f<BR />OK: write reg. OTP_PWRDN_DLY1 = 0x00<BR />OK: write reg. OTP_PWRDN_DLY2 = 0x81<BR />OK: write reg. OTP_PWRUP_CTRL = 0x02<BR />OK: write reg. OTP_RESETBMCU_PWRUP = 0x00<BR />OK: write reg. OTP_PGOOD_PWRUP = 0x00<BR />OK: write reg. OTP_SW1_VOLT = 0x20<BR />OK: write reg. OTP_SW1_PWRUP = 0x15<BR />OK: write reg. OTP_SW1_CONFIG1 = 0x53<BR />OK: write reg. OTP_SW1_CONFIG2 = 0x09<BR />OK: write reg. OTP_SW2_VOLT = 0x70<BR />OK: write reg. OTP_SW2_PWRUP = 0x15<BR />OK: write reg. OTP_SW2_CONFIG1 = 0x53<BR />OK: write reg. OTP_SW2_CONFIG2 = 0x29<BR />OK: write reg. OTP_SW3_VOLT = 0x60<BR />OK: write reg. OTP_SW3_PWRUP = 0x3d<BR />OK: write reg. OTP_SW3_CONFIG1 = 0x53<BR />OK: write reg. OTP_SW3_CONFIG2 = 0x3b<BR />OK: write reg. OTP_SW4_VOLT = 0xb1<BR />OK: write reg. OTP_SW4_PWRUP = 0x47<BR />OK: write reg. OTP_SW4_CONFIG1 = 0x53<BR />OK: write reg. OTP_SW4_CONFIG2 = 0x2b<BR />OK: write reg. OTP_SW5_VOLT = 0xb0<BR />OK: write reg. OTP_SW5_PWRUP = 0x51<BR />OK: write reg. OTP_SW5_CONFIG1 = 0x53<BR />OK: write reg. OTP_SW5_CONFIG2 = 0x33<BR />OK: write reg. OTP_SW6_VOLT = 0x38<BR />OK: write reg. OTP_SW6_PWRUP = 0x51<BR />OK: write reg. OTP_SW6_CONFIG1 = 0x53<BR />OK: write reg. OTP_SW6_CONFIG2 = 0x13<BR />OK: write reg. OTP_SW7_VOLT = 0x15<BR />OK: write reg. OTP_SW7_PWRUP = 0x47<BR />OK: write reg. OTP_SW7_CONFIG1 = 0x53<BR />OK: write reg. OTP_SW7_CONFIG2 = 0x03<BR />OK: write reg. OTP_LDO1_VOLT = 0x52<BR />OK: write reg. OTP_LDO1_PWRUP = 0x5b<BR />OK: write reg. OTP_LDO1_CONFIG = 0x06<BR />OK: write reg. OTP_LDO2_VOLT = 0x50<BR />OK: write reg. OTP_LDO2_PWRUP = 0x00<BR />OK: write reg. OTP_LDO2_CONFIG = 0x12<BR />OK: write reg. OTP_LDO3_VOLT = 0x52<BR />OK: write reg. OTP_LDO3_PWRUP = 0x65<BR />OK: write reg. OTP_LDO3_CONFIG = 0x06<BR />OK: write reg. OTP_LDO4_VOLT = 0x52<BR />OK: write reg. OTP_LDO4_PWRUP = 0x6f<BR />OK: write reg. OTP_LDO4_CONFIG = 0x06<BR />OK: write reg. OTP_VSNVS_CONFIG = 0x00<BR />OK: write reg. OTP_OV_BYPASS1 = 0x7f<BR />OK: write reg. OTP_OV_BYPASS2 = 0x0f<BR />OK: write reg. OTP_UV_BYPASS1 = 0x7f<BR />OK: write reg. OTP_UV_BYPASS2 = 0x0f<BR />OK: write reg. OTP_ILIM_BYPASS1 = 0x7f<BR />OK: write reg. OTP_ILIM_BYPASS2 = 0x0f<BR />OK: write reg. OTP_PROG_IDH = 0x00<BR />OK: write reg. OTP_PROG_IDL = 0x00<BR />OK: write reg. OTP_DEBUG1 = 0x01<BR />OK: write reg. OTP_SW_COMP1 = 0x00<BR />OK: write reg. OTP_SW_COMP2 = 0x00<BR />OK: write reg. OTP_SW_COMP3 = 0x00</P><P>// CONFIGURE OTP CONTROLLER<BR />OK: write reg. FCMD = 0x80<BR />OK: write reg. FADDR_START = 0x00<BR />OK: write reg. FDATA = 0xac<BR />OK: write reg. FCMD = 0xa9<BR />OK: write reg. FADDR_START = 0x02<BR />OK: write reg. FDATA = 0xdc<BR />OK: write reg. FCMD = 0xa9<BR />OK: write reg. FADDR_START = 0x08<BR />OK: write reg. FDATA = 0x38<BR />OK: write reg. FCMD = 0xa9<BR />OK: write reg. FADDR_START = 0x09<BR />OK: write reg. FDATA = 0xdc<BR />OK: write reg. FCMD = 0xa9<BR />OK: write reg. FADDR_START = 0x0c<BR />OK: write reg. FDATA = 0xd2<BR />OK: write reg. FCMD = 0xa9</P><P>OK: write reg. MAX_PGM_TRIES = 0x08<BR />OK: write reg. MRR_SVDR_IN = 0x13<BR />OK: write reg. MR_TEST_H = 0x00<BR />OK: write reg. MR_TEST_L = 0x02<BR />OK: write reg. MREF_TEST_H = 0x00<BR />OK: write reg. MREF_TEST_L = 0x00<BR />OK: write reg. PULSE_DUR_1 = 0xbb<BR />OK: write reg. PULSE_DUR_2 = 0x08<BR />OK: write reg. FADDR_START = 0x00<BR />OK: write reg. FADDR_STOP = 0x48</P><P>// SET CRC VALUES<BR />OK: write reg. FCMD = 0xa5<BR />OK: write reg. FCMD = 0xa4<BR />Error: Command execution failed<BR />Error: Command execution failed<BR />Error: Command execution failed</P><P>// START FUSE PROGRAMMING<BR />OK: write reg. FCMD = 0x96<BR />Error: Command execution failed<BR />Error: Command execution failed<BR />Error: Command execution failed<BR />Error: Command execution failed<BR />Error: Command execution failed<BR />Error: Command execution failed<BR />Error: Command execution failed<BR />Error: Command execution failed</P><P>// BURN BOOT ENABLE AND WRITE PROTECT BITS<BR />OK: write reg. FADDR_STOP = 0xff<BR />OK: write reg. FADDR_START = 0xfe<BR />OK: write reg. FDATA = 0xaa<BR />OK: write reg. FCMD = 0x87<BR />Error: Command execution failed<BR />Error: Command execution failed<BR />OK: write reg. FADDR_START = 0xff<BR />OK: write reg. FDATA = 0x55<BR />OK: write reg. FCMD = 0x87<BR />Error: Command execution failed<BR />Error: Command execution failed<BR />OK: write reg. FADDR_START = 0xfc<BR />OK: write reg. FDATA = 0xaa<BR />OK: write reg. FCMD = 0x87<BR />Error: Command execution failed<BR />Error: Command execution failed<BR />OK: write reg. FADDR_START = 0xfd<BR />OK: write reg. FDATA = 0x55<BR />OK: write reg. FCMD = 0x87<BR />Error: Command execution failed<BR />Error: Command execution failed<BR />Error: Command execution failed</P><P>OK: set USBEN digital pin = LOW<BR />OK: set BSTEN digital pin = LOW<BR />OK: set VDDOTPEN digital pin = LOW</P><P>//Verify Mirror Registers = Fuse Value<BR />Error: Command execution failed<BR />OK: write reg. FADDR_START = 0x00<BR />OK: write reg. FADDR_STOP = 0x48<BR />OK: write reg. FCMD = 0xab<BR />OK: write reg. FCMD = 0xa0<BR />OK: write reg. FCMD = 0xa1<BR />OK: write reg. FCMD = 0xa4<BR />Error: Command execution failed<BR />Error: Command execution failed<BR />Error: Command execution failed<BR />Error: Command execution failed</P><P>//If SECT_STATUS = 0x3F &amp; FSTATUS = 0x00 part is programmed correctly.<BR />//Verify CRC_LSB and CRC_MSB match the values in section "SET CRC VALUES" .<BR />OK: set TBBEN digital pin = LOW</P><P>TBB result:</P><P>OK: set PWRON digital pin = LOW<BR />OK: set WDI digital pin = LOW<BR />OK: set TBBEN digital pin = HIGH<BR />OK: write reg. OTP_FSOB_SELECT = 0x00<BR />OK: write reg. OTP_I2C = 0x00<BR />OK: write reg. OTP_CTRL1 = 0x0a<BR />OK: write reg. OTP_CTRL2 = 0x41<BR />OK: write reg. OTP_CTRL3 = 0x41<BR />OK: write reg. OTP_FREQ_CTRL = 0x80<BR />OK: write reg. OTP_COINCELL_CTRL = 0x0b<BR />OK: write reg. OTP_PWRON = 0x00<BR />OK: write reg. OTP_WD_CONFIG = 0x10<BR />OK: write reg. OTP_WD_EXPIRE = 0x07<BR />OK: write reg. OTP_WD_COUNTER = 0xaf<BR />OK: write reg. OTP_FAULT_COUNTER = 0xf0<BR />OK: write reg. OTP_FAULT_TIMERS = 0x7f<BR />OK: write reg. OTP_PWRDN_DLY1 = 0x00<BR />OK: write reg. OTP_PWRDN_DLY2 = 0x81<BR />OK: write reg. OTP_PWRUP_CTRL = 0x02<BR />OK: write reg. OTP_RESETBMCU_PWRUP = 0x00<BR />OK: write reg. OTP_PGOOD_PWRUP = 0x00<BR />OK: write reg. OTP_SW1_VOLT = 0x20<BR />OK: write reg. OTP_SW1_PWRUP = 0x15<BR />OK: write reg. OTP_SW1_CONFIG1 = 0x53<BR />OK: write reg. OTP_SW1_CONFIG2 = 0x09<BR />OK: write reg. OTP_SW2_VOLT = 0x70<BR />OK: write reg. OTP_SW2_PWRUP = 0x15<BR />OK: write reg. OTP_SW2_CONFIG1 = 0x53<BR />OK: write reg. OTP_SW2_CONFIG2 = 0x29<BR />OK: write reg. OTP_SW3_VOLT = 0x60<BR />OK: write reg. OTP_SW3_PWRUP = 0x3d<BR />OK: write reg. OTP_SW3_CONFIG1 = 0x53<BR />OK: write reg. OTP_SW3_CONFIG2 = 0x3b<BR />OK: write reg. OTP_SW4_VOLT = 0xb1<BR />OK: write reg. OTP_SW4_PWRUP = 0x47<BR />OK: write reg. OTP_SW4_CONFIG1 = 0x53<BR />OK: write reg. OTP_SW4_CONFIG2 = 0x2b<BR />OK: write reg. OTP_SW5_VOLT = 0xb0<BR />OK: write reg. OTP_SW5_PWRUP = 0x51<BR />OK: write reg. OTP_SW5_CONFIG1 = 0x53<BR />OK: write reg. OTP_SW5_CONFIG2 = 0x33<BR />OK: write reg. OTP_SW6_VOLT = 0x38<BR />OK: write reg. OTP_SW6_PWRUP = 0x51<BR />OK: write reg. OTP_SW6_CONFIG1 = 0x53<BR />OK: write reg. OTP_SW6_CONFIG2 = 0x13<BR />OK: write reg. OTP_SW7_VOLT = 0x15<BR />OK: write reg. OTP_SW7_PWRUP = 0x47<BR />OK: write reg. OTP_SW7_CONFIG1 = 0x53<BR />OK: write reg. OTP_SW7_CONFIG2 = 0x03<BR />OK: write reg. OTP_LDO1_VOLT = 0x52<BR />OK: write reg. OTP_LDO1_PWRUP = 0x5b<BR />OK: write reg. OTP_LDO1_CONFIG = 0x06<BR />OK: write reg. OTP_LDO2_VOLT = 0x50<BR />OK: write reg. OTP_LDO2_PWRUP = 0x00<BR />OK: write reg. OTP_LDO2_CONFIG = 0x12<BR />OK: write reg. OTP_LDO3_VOLT = 0x52<BR />OK: write reg. OTP_LDO3_PWRUP = 0x65<BR />OK: write reg. OTP_LDO3_CONFIG = 0x06<BR />OK: write reg. OTP_LDO4_VOLT = 0x52<BR />OK: write reg. OTP_LDO4_PWRUP = 0x6f<BR />OK: write reg. OTP_LDO4_CONFIG = 0x06<BR />OK: write reg. OTP_VSNVS_CONFIG = 0x00<BR />OK: write reg. OTP_OV_BYPASS1 = 0x7f<BR />OK: write reg. OTP_OV_BYPASS2 = 0x0f<BR />OK: write reg. OTP_UV_BYPASS1 = 0x7f<BR />OK: write reg. OTP_UV_BYPASS2 = 0x0f<BR />OK: write reg. OTP_ILIM_BYPASS1 = 0x7f<BR />OK: write reg. OTP_ILIM_BYPASS2 = 0x0f<BR />OK: write reg. OTP_PROG_IDH = 0x00<BR />OK: write reg. OTP_PROG_IDL = 0x00<BR />OK: write reg. OTP_DEBUG1 = 0x01<BR />OK: write reg. OTP_SW_COMP1 = 0x00<BR />OK: write reg. OTP_SW_COMP2 = 0x00<BR />OK: write reg. OTP_SW_COMP3 = 0x00<BR />OK: write reg. FCMD = 0xa5<BR />OK: write reg. FCMD = 0xa4<BR />OK: write reg. TEST_FLAGS = 0x07<BR />OK: set TBBEN digital pin = LOW<BR />OK: set PWRON digital pin = HIGH</P><P>&nbsp;</P><P>&nbsp;</P><P>&nbsp;</P> Tue, 27 Jun 2023 01:23:03 GMT jjaa 2023-06-27T01:23:03Z https://community.nxp.com/t5/Power-Management/KITPF8200FRDPGM-error/m-p/1676441#M2761 <P>i use KITPF8200FRDPGM and MC33PF8200</P><P>TBB Mode is Possibe But OTP Mode is not possible</P><P>here is my script&nbsp;</P><P>OTP:</P><P>&nbsp;</P><P>SET_DPIN:PF8200:PWRON:low<BR />SET_DPIN:PF8200:WDI:low<BR />SET_DPIN:PF8200:TBBEN:high<BR />SET_DPIN:PF8200:USBEN:high<BR />SET_DPIN:PF8200:BSTEN:high<BR />SET_DPIN:PF8200:VDDOTPEN:high<BR />SET_REG:PF8200:OTP_MIRROR:OTP_FSOB_SELECT:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_I2C:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_CTRL1:0x0A<BR />SET_REG:PF8200:OTP_MIRROR:OTP_CTRL2:0x41<BR />SET_REG:PF8200:OTP_MIRROR:OTP_CTRL3:0x41<BR />SET_REG:PF8200:OTP_MIRROR:OTP_FREQ_CTRL:0x80<BR />SET_REG:PF8200:OTP_MIRROR:OTP_COINCELL_CTRL:0x0B<BR />SET_REG:PF8200:OTP_MIRROR:OTP_PWRON:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_WD_CONFIG:0x10<BR />SET_REG:PF8200:OTP_MIRROR:OTP_WD_EXPIRE:0x07<BR />SET_REG:PF8200:OTP_MIRROR:OTP_WD_COUNTER:0xAF<BR />SET_REG:PF8200:OTP_MIRROR:OTP_FAULT_COUNTER:0xF0<BR />SET_REG:PF8200:OTP_MIRROR:OTP_FAULT_TIMERS:0x7F<BR />SET_REG:PF8200:OTP_MIRROR:OTP_PWRDN_DLY1:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_PWRDN_DLY2:0x81<BR />SET_REG:PF8200:OTP_MIRROR:OTP_PWRUP_CTRL:0x02<BR />SET_REG:PF8200:OTP_MIRROR:OTP_RESETBMCU_PWRUP:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_PGOOD_PWRUP:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW1_VOLT:0x20<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW1_PWRUP:0x15<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW1_CONFIG1:0x53<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW1_CONFIG2:0x09<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW2_VOLT:0x70<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW2_PWRUP:0x15<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW2_CONFIG1:0x53<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW2_CONFIG2:0x29<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW3_VOLT:0x60<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW3_PWRUP:0x3D<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW3_CONFIG1:0x53<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW3_CONFIG2:0x3B<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW4_VOLT:0xB1<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW4_PWRUP:0x47<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW4_CONFIG1:0x53<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW4_CONFIG2:0x2B<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW5_VOLT:0xB0<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW5_PWRUP:0x51<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW5_CONFIG1:0x53<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW5_CONFIG2:0x33<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW6_VOLT:0x38<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW6_PWRUP:0x51<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW6_CONFIG1:0x53<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW6_CONFIG2:0x13<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW7_VOLT:0x15<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW7_PWRUP:0x47<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW7_CONFIG1:0x53<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW7_CONFIG2:0x03<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO1_VOLT:0x52<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO1_PWRUP:0x5B<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO1_CONFIG:0x06<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO2_VOLT:0x50<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO2_PWRUP:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO2_CONFIG:0x12<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO3_VOLT:0x52<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO3_PWRUP:0x65<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO3_CONFIG:0x06<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO4_VOLT:0x52<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO4_PWRUP:0x6F<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO4_CONFIG:0x06<BR />SET_REG:PF8200:OTP_MIRROR:OTP_VSNVS_CONFIG:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_OV_BYPASS1:0x7F<BR />SET_REG:PF8200:OTP_MIRROR:OTP_OV_BYPASS2:0x0F<BR />SET_REG:PF8200:OTP_MIRROR:OTP_UV_BYPASS1:0x7F<BR />SET_REG:PF8200:OTP_MIRROR:OTP_UV_BYPASS2:0x0F<BR />SET_REG:PF8200:OTP_MIRROR:OTP_ILIM_BYPASS1:0x7F<BR />SET_REG:PF8200:OTP_MIRROR:OTP_ILIM_BYPASS2:0x0F<BR />SET_REG:PF8200:OTP_MIRROR:OTP_PROG_IDH:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_PROG_IDL:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_DEBUG1:0x01<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW_COMP1:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW_COMP2:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW_COMP3:0x00</P><P>// CONFIGURE OTP CONTROLLER<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0x80<BR />SET_REG:PF8200:OTP_PAGE2:FADDR_START:0x00<BR />SET_REG:PF8200:OTP_PAGE2:FDATA:0xAC<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0xA9<BR />SET_REG:PF8200:OTP_PAGE2:FADDR_START:0x02<BR />SET_REG:PF8200:OTP_PAGE2:FDATA:0xDC<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0xA9<BR />SET_REG:PF8200:OTP_PAGE2:FADDR_START:0x08<BR />SET_REG:PF8200:OTP_PAGE2:FDATA:0x38<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0xA9<BR />SET_REG:PF8200:OTP_PAGE2:FADDR_START:0x09<BR />SET_REG:PF8200:OTP_PAGE2:FDATA:0xDC<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0xA9<BR />SET_REG:PF8200:OTP_PAGE2:FADDR_START:0x0C<BR />SET_REG:PF8200:OTP_PAGE2:FDATA:0xD2<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0xA9</P><P>SET_REG:PF8200:OTP_PAGE2:MAX_PGM_TRIES:0x08<BR />SET_REG:PF8200:OTP_PAGE2:MRR_SVDR_IN:0x13<BR />SET_REG:PF8200:OTP_PAGE2:MR_TEST_H:0x00<BR />SET_REG:PF8200:OTP_PAGE2:MR_TEST_L:0x02<BR />SET_REG:PF8200:OTP_PAGE2:MREF_TEST_H:0x00<BR />SET_REG:PF8200:OTP_PAGE2:MREF_TEST_L:0x00<BR />SET_REG:PF8200:OTP_PAGE2:PULSE_DUR_1:0xBB<BR />SET_REG:PF8200:OTP_PAGE2:PULSE_DUR_2:0x08<BR />SET_REG:PF8200:OTP_PAGE2:FADDR_START:0x00<BR />SET_REG:PF8200:OTP_PAGE2:FADDR_STOP:0x48</P><P>// SET CRC VALUES<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0xA5<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0xA4<BR />GET_REG:PF8200:OTP_MIRROR:OTP_S0_CRC_LSB<BR />GET_REG:PF8200:OTP_MIRROR:OTP_S0_CRC_MSB<BR />GET_REG:PF8200:OTP_PAGE2:SECT_STATUS</P><P>// START FUSE PROGRAMMING<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0x96<BR />GET_REG:PF8200:OTP_PAGE2:FSTATUS<BR />GET_REG:PF8200:OTP_PAGE2:FSTATUS<BR />GET_REG:PF8200:OTP_PAGE2:FSTATUS<BR />GET_REG:PF8200:OTP_PAGE2:FSTATUS<BR />GET_REG:PF8200:OTP_PAGE2:FSTATUS<BR />GET_REG:PF8200:OTP_PAGE2:FSTATUS<BR />GET_REG:PF8200:OTP_PAGE2:FSTATUS<BR />GET_REG:PF8200:OTP_PAGE2:FSTATUS</P><P>// BURN BOOT ENABLE AND WRITE PROTECT BITS<BR />SET_REG:PF8200:OTP_PAGE2:FADDR_STOP:0xFF<BR />SET_REG:PF8200:OTP_PAGE2:FADDR_START:0xFE<BR />SET_REG:PF8200:OTP_PAGE2:FDATA:0xAA<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0x87<BR />GET_REG:PF8200:OTP_PAGE2:FSTATUS<BR />GET_REG:PF8200:OTP_PAGE2:FSTATUS<BR />SET_REG:PF8200:OTP_PAGE2:FADDR_START:0xFF<BR />SET_REG:PF8200:OTP_PAGE2:FDATA:0x55<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0x87<BR />GET_REG:PF8200:OTP_PAGE2:FSTATUS<BR />GET_REG:PF8200:OTP_PAGE2:FSTATUS<BR />SET_REG:PF8200:OTP_PAGE2:FADDR_START:0xFC<BR />SET_REG:PF8200:OTP_PAGE2:FDATA:0xAA<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0x87<BR />GET_REG:PF8200:OTP_PAGE2:FSTATUS<BR />GET_REG:PF8200:OTP_PAGE2:FSTATUS<BR />SET_REG:PF8200:OTP_PAGE2:FADDR_START:0xFD<BR />SET_REG:PF8200:OTP_PAGE2:FDATA:0x55<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0x87<BR />GET_REG:PF8200:OTP_PAGE2:FSTATUS<BR />GET_REG:PF8200:OTP_PAGE2:FSTATUS<BR />GET_REG:PF8200:OTP_PAGE2:SECT_STATUS</P><P>SET_DPIN:PF8200:USBEN:low<BR />SET_DPIN:PF8200:BSTEN:low<BR />SET_DPIN:PF8200:VDDOTPEN:low</P><P>//Verify Mirror Registers = Fuse Value<BR />GET_REG:PF8200:functional:DEVICE_ID<BR />SET_REG:PF8200:OTP_PAGE2:FADDR_START:0x00<BR />SET_REG:PF8200:OTP_PAGE2:FADDR_STOP:0x48<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0xAB<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0xA0<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0xA1<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0xA4<BR />GET_REG:PF8200:OTP_MIRROR:OTP_S0_CRC_LSB<BR />GET_REG:PF8200:OTP_MIRROR:OTP_S0_CRC_MSB<BR />GET_REG:PF8200:OTP_PAGE2:SECT_STATUS<BR />GET_REG:PF8200:OTP_PAGE2:FSTATUS</P><P>//If SECT_STATUS = 0x3F &amp; FSTATUS = 0x00 part is programmed correctly.<BR />//Verify CRC_LSB and CRC_MSB match the values in section "SET CRC VALUES" .<BR />SET_DPIN:PF8200:TBBEN:low</P><P>&nbsp;</P><P>TBB:</P><P>SET_DPIN:PF8200:PWRON:low<BR />SET_DPIN:PF8200:WDI:low<BR />SET_DPIN:PF8200:TBBEN:high<BR />SET_REG:PF8200:OTP_MIRROR:OTP_FSOB_SELECT:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_I2C:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_CTRL1:0x0A<BR />SET_REG:PF8200:OTP_MIRROR:OTP_CTRL2:0x41<BR />SET_REG:PF8200:OTP_MIRROR:OTP_CTRL3:0x41<BR />SET_REG:PF8200:OTP_MIRROR:OTP_FREQ_CTRL:0x80<BR />SET_REG:PF8200:OTP_MIRROR:OTP_COINCELL_CTRL:0x0B<BR />SET_REG:PF8200:OTP_MIRROR:OTP_PWRON:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_WD_CONFIG:0x10<BR />SET_REG:PF8200:OTP_MIRROR:OTP_WD_EXPIRE:0x07<BR />SET_REG:PF8200:OTP_MIRROR:OTP_WD_COUNTER:0xAF<BR />SET_REG:PF8200:OTP_MIRROR:OTP_FAULT_COUNTER:0xF0<BR />SET_REG:PF8200:OTP_MIRROR:OTP_FAULT_TIMERS:0x7F<BR />SET_REG:PF8200:OTP_MIRROR:OTP_PWRDN_DLY1:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_PWRDN_DLY2:0x81<BR />SET_REG:PF8200:OTP_MIRROR:OTP_PWRUP_CTRL:0x02<BR />SET_REG:PF8200:OTP_MIRROR:OTP_RESETBMCU_PWRUP:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_PGOOD_PWRUP:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW1_VOLT:0x20<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW1_PWRUP:0x15<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW1_CONFIG1:0x53<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW1_CONFIG2:0x09<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW2_VOLT:0x70<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW2_PWRUP:0x15<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW2_CONFIG1:0x53<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW2_CONFIG2:0x29<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW3_VOLT:0x60<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW3_PWRUP:0x3D<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW3_CONFIG1:0x53<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW3_CONFIG2:0x3B<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW4_VOLT:0xB1<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW4_PWRUP:0x47<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW4_CONFIG1:0x53<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW4_CONFIG2:0x2B<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW5_VOLT:0xB0<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW5_PWRUP:0x51<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW5_CONFIG1:0x53<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW5_CONFIG2:0x33<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW6_VOLT:0x38<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW6_PWRUP:0x51<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW6_CONFIG1:0x53<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW6_CONFIG2:0x13<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW7_VOLT:0x15<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW7_PWRUP:0x47<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW7_CONFIG1:0x53<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW7_CONFIG2:0x03<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO1_VOLT:0x52<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO1_PWRUP:0x5B<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO1_CONFIG:0x06<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO2_VOLT:0x50<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO2_PWRUP:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO2_CONFIG:0x12<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO3_VOLT:0x52<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO3_PWRUP:0x65<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO3_CONFIG:0x06<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO4_VOLT:0x52<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO4_PWRUP:0x6F<BR />SET_REG:PF8200:OTP_MIRROR:OTP_LDO4_CONFIG:0x06<BR />SET_REG:PF8200:OTP_MIRROR:OTP_VSNVS_CONFIG:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_OV_BYPASS1:0x7F<BR />SET_REG:PF8200:OTP_MIRROR:OTP_OV_BYPASS2:0x0F<BR />SET_REG:PF8200:OTP_MIRROR:OTP_UV_BYPASS1:0x7F<BR />SET_REG:PF8200:OTP_MIRROR:OTP_UV_BYPASS2:0x0F<BR />SET_REG:PF8200:OTP_MIRROR:OTP_ILIM_BYPASS1:0x7F<BR />SET_REG:PF8200:OTP_MIRROR:OTP_ILIM_BYPASS2:0x0F<BR />SET_REG:PF8200:OTP_MIRROR:OTP_PROG_IDH:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_PROG_IDL:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_DEBUG1:0x01<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW_COMP1:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW_COMP2:0x00<BR />SET_REG:PF8200:OTP_MIRROR:OTP_SW_COMP3:0x00<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0xA5<BR />SET_REG:PF8200:OTP_PAGE2:FCMD:0xA4<BR />SET_REG:PF8200:functional:TEST_FLAGS:0x07<BR />SET_DPIN:PF8200:TBBEN:low<BR />SET_DPIN:PF8200:PWRON:high</P><P>&nbsp;</P><P>OTP Result:</P><P>OK: set PWRON digital pin = LOW<BR />OK: set WDI digital pin = LOW<BR />OK: set TBBEN digital pin = HIGH<BR />OK: set USBEN digital pin = HIGH<BR />OK: set BSTEN digital pin = HIGH<BR />OK: set VDDOTPEN digital pin = HIGH<BR />OK: write reg. OTP_FSOB_SELECT = 0x00<BR />OK: write reg. OTP_I2C = 0x00<BR />OK: write reg. OTP_CTRL1 = 0x0a<BR />OK: write reg. OTP_CTRL2 = 0x41<BR />OK: write reg. OTP_CTRL3 = 0x41<BR />OK: write reg. OTP_FREQ_CTRL = 0x80<BR />OK: write reg. OTP_COINCELL_CTRL = 0x0b<BR />OK: write reg. OTP_PWRON = 0x00<BR />OK: write reg. OTP_WD_CONFIG = 0x10<BR />OK: write reg. OTP_WD_EXPIRE = 0x07<BR />OK: write reg. OTP_WD_COUNTER = 0xaf<BR />OK: write reg. OTP_FAULT_COUNTER = 0xf0<BR />OK: write reg. OTP_FAULT_TIMERS = 0x7f<BR />OK: write reg. OTP_PWRDN_DLY1 = 0x00<BR />OK: write reg. OTP_PWRDN_DLY2 = 0x81<BR />OK: write reg. OTP_PWRUP_CTRL = 0x02<BR />OK: write reg. OTP_RESETBMCU_PWRUP = 0x00<BR />OK: write reg. OTP_PGOOD_PWRUP = 0x00<BR />OK: write reg. OTP_SW1_VOLT = 0x20<BR />OK: write reg. OTP_SW1_PWRUP = 0x15<BR />OK: write reg. OTP_SW1_CONFIG1 = 0x53<BR />OK: write reg. OTP_SW1_CONFIG2 = 0x09<BR />OK: write reg. OTP_SW2_VOLT = 0x70<BR />OK: write reg. OTP_SW2_PWRUP = 0x15<BR />OK: write reg. OTP_SW2_CONFIG1 = 0x53<BR />OK: write reg. OTP_SW2_CONFIG2 = 0x29<BR />OK: write reg. OTP_SW3_VOLT = 0x60<BR />OK: write reg. OTP_SW3_PWRUP = 0x3d<BR />OK: write reg. OTP_SW3_CONFIG1 = 0x53<BR />OK: write reg. OTP_SW3_CONFIG2 = 0x3b<BR />OK: write reg. OTP_SW4_VOLT = 0xb1<BR />OK: write reg. OTP_SW4_PWRUP = 0x47<BR />OK: write reg. OTP_SW4_CONFIG1 = 0x53<BR />OK: write reg. OTP_SW4_CONFIG2 = 0x2b<BR />OK: write reg. OTP_SW5_VOLT = 0xb0<BR />OK: write reg. OTP_SW5_PWRUP = 0x51<BR />OK: write reg. OTP_SW5_CONFIG1 = 0x53<BR />OK: write reg. OTP_SW5_CONFIG2 = 0x33<BR />OK: write reg. OTP_SW6_VOLT = 0x38<BR />OK: write reg. OTP_SW6_PWRUP = 0x51<BR />OK: write reg. OTP_SW6_CONFIG1 = 0x53<BR />OK: write reg. OTP_SW6_CONFIG2 = 0x13<BR />OK: write reg. OTP_SW7_VOLT = 0x15<BR />OK: write reg. OTP_SW7_PWRUP = 0x47<BR />OK: write reg. OTP_SW7_CONFIG1 = 0x53<BR />OK: write reg. OTP_SW7_CONFIG2 = 0x03<BR />OK: write reg. OTP_LDO1_VOLT = 0x52<BR />OK: write reg. OTP_LDO1_PWRUP = 0x5b<BR />OK: write reg. OTP_LDO1_CONFIG = 0x06<BR />OK: write reg. OTP_LDO2_VOLT = 0x50<BR />OK: write reg. OTP_LDO2_PWRUP = 0x00<BR />OK: write reg. OTP_LDO2_CONFIG = 0x12<BR />OK: write reg. OTP_LDO3_VOLT = 0x52<BR />OK: write reg. OTP_LDO3_PWRUP = 0x65<BR />OK: write reg. OTP_LDO3_CONFIG = 0x06<BR />OK: write reg. OTP_LDO4_VOLT = 0x52<BR />OK: write reg. OTP_LDO4_PWRUP = 0x6f<BR />OK: write reg. OTP_LDO4_CONFIG = 0x06<BR />OK: write reg. OTP_VSNVS_CONFIG = 0x00<BR />OK: write reg. OTP_OV_BYPASS1 = 0x7f<BR />OK: write reg. OTP_OV_BYPASS2 = 0x0f<BR />OK: write reg. OTP_UV_BYPASS1 = 0x7f<BR />OK: write reg. OTP_UV_BYPASS2 = 0x0f<BR />OK: write reg. OTP_ILIM_BYPASS1 = 0x7f<BR />OK: write reg. OTP_ILIM_BYPASS2 = 0x0f<BR />OK: write reg. OTP_PROG_IDH = 0x00<BR />OK: write reg. OTP_PROG_IDL = 0x00<BR />OK: write reg. OTP_DEBUG1 = 0x01<BR />OK: write reg. OTP_SW_COMP1 = 0x00<BR />OK: write reg. OTP_SW_COMP2 = 0x00<BR />OK: write reg. OTP_SW_COMP3 = 0x00</P><P>// CONFIGURE OTP CONTROLLER<BR />OK: write reg. FCMD = 0x80<BR />OK: write reg. FADDR_START = 0x00<BR />OK: write reg. FDATA = 0xac<BR />OK: write reg. FCMD = 0xa9<BR />OK: write reg. FADDR_START = 0x02<BR />OK: write reg. FDATA = 0xdc<BR />OK: write reg. FCMD = 0xa9<BR />OK: write reg. FADDR_START = 0x08<BR />OK: write reg. FDATA = 0x38<BR />OK: write reg. FCMD = 0xa9<BR />OK: write reg. FADDR_START = 0x09<BR />OK: write reg. FDATA = 0xdc<BR />OK: write reg. FCMD = 0xa9<BR />OK: write reg. FADDR_START = 0x0c<BR />OK: write reg. FDATA = 0xd2<BR />OK: write reg. FCMD = 0xa9</P><P>OK: write reg. MAX_PGM_TRIES = 0x08<BR />OK: write reg. MRR_SVDR_IN = 0x13<BR />OK: write reg. MR_TEST_H = 0x00<BR />OK: write reg. MR_TEST_L = 0x02<BR />OK: write reg. MREF_TEST_H = 0x00<BR />OK: write reg. MREF_TEST_L = 0x00<BR />OK: write reg. PULSE_DUR_1 = 0xbb<BR />OK: write reg. PULSE_DUR_2 = 0x08<BR />OK: write reg. FADDR_START = 0x00<BR />OK: write reg. FADDR_STOP = 0x48</P><P>// SET CRC VALUES<BR />OK: write reg. FCMD = 0xa5<BR />OK: write reg. FCMD = 0xa4<BR />Error: Command execution failed<BR />Error: Command execution failed<BR />Error: Command execution failed</P><P>// START FUSE PROGRAMMING<BR />OK: write reg. FCMD = 0x96<BR />Error: Command execution failed<BR />Error: Command execution failed<BR />Error: Command execution failed<BR />Error: Command execution failed<BR />Error: Command execution failed<BR />Error: Command execution failed<BR />Error: Command execution failed<BR />Error: Command execution failed</P><P>// BURN BOOT ENABLE AND WRITE PROTECT BITS<BR />OK: write reg. FADDR_STOP = 0xff<BR />OK: write reg. FADDR_START = 0xfe<BR />OK: write reg. FDATA = 0xaa<BR />OK: write reg. FCMD = 0x87<BR />Error: Command execution failed<BR />Error: Command execution failed<BR />OK: write reg. FADDR_START = 0xff<BR />OK: write reg. FDATA = 0x55<BR />OK: write reg. FCMD = 0x87<BR />Error: Command execution failed<BR />Error: Command execution failed<BR />OK: write reg. FADDR_START = 0xfc<BR />OK: write reg. FDATA = 0xaa<BR />OK: write reg. FCMD = 0x87<BR />Error: Command execution failed<BR />Error: Command execution failed<BR />OK: write reg. FADDR_START = 0xfd<BR />OK: write reg. FDATA = 0x55<BR />OK: write reg. FCMD = 0x87<BR />Error: Command execution failed<BR />Error: Command execution failed<BR />Error: Command execution failed</P><P>OK: set USBEN digital pin = LOW<BR />OK: set BSTEN digital pin = LOW<BR />OK: set VDDOTPEN digital pin = LOW</P><P>//Verify Mirror Registers = Fuse Value<BR />Error: Command execution failed<BR />OK: write reg. FADDR_START = 0x00<BR />OK: write reg. FADDR_STOP = 0x48<BR />OK: write reg. FCMD = 0xab<BR />OK: write reg. FCMD = 0xa0<BR />OK: write reg. FCMD = 0xa1<BR />OK: write reg. FCMD = 0xa4<BR />Error: Command execution failed<BR />Error: Command execution failed<BR />Error: Command execution failed<BR />Error: Command execution failed</P><P>//If SECT_STATUS = 0x3F &amp; FSTATUS = 0x00 part is programmed correctly.<BR />//Verify CRC_LSB and CRC_MSB match the values in section "SET CRC VALUES" .<BR />OK: set TBBEN digital pin = LOW</P><P>TBB result:</P><P>OK: set PWRON digital pin = LOW<BR />OK: set WDI digital pin = LOW<BR />OK: set TBBEN digital pin = HIGH<BR />OK: write reg. OTP_FSOB_SELECT = 0x00<BR />OK: write reg. OTP_I2C = 0x00<BR />OK: write reg. OTP_CTRL1 = 0x0a<BR />OK: write reg. OTP_CTRL2 = 0x41<BR />OK: write reg. OTP_CTRL3 = 0x41<BR />OK: write reg. OTP_FREQ_CTRL = 0x80<BR />OK: write reg. OTP_COINCELL_CTRL = 0x0b<BR />OK: write reg. OTP_PWRON = 0x00<BR />OK: write reg. OTP_WD_CONFIG = 0x10<BR />OK: write reg. OTP_WD_EXPIRE = 0x07<BR />OK: write reg. OTP_WD_COUNTER = 0xaf<BR />OK: write reg. OTP_FAULT_COUNTER = 0xf0<BR />OK: write reg. OTP_FAULT_TIMERS = 0x7f<BR />OK: write reg. OTP_PWRDN_DLY1 = 0x00<BR />OK: write reg. OTP_PWRDN_DLY2 = 0x81<BR />OK: write reg. OTP_PWRUP_CTRL = 0x02<BR />OK: write reg. OTP_RESETBMCU_PWRUP = 0x00<BR />OK: write reg. OTP_PGOOD_PWRUP = 0x00<BR />OK: write reg. OTP_SW1_VOLT = 0x20<BR />OK: write reg. OTP_SW1_PWRUP = 0x15<BR />OK: write reg. OTP_SW1_CONFIG1 = 0x53<BR />OK: write reg. OTP_SW1_CONFIG2 = 0x09<BR />OK: write reg. OTP_SW2_VOLT = 0x70<BR />OK: write reg. OTP_SW2_PWRUP = 0x15<BR />OK: write reg. OTP_SW2_CONFIG1 = 0x53<BR />OK: write reg. OTP_SW2_CONFIG2 = 0x29<BR />OK: write reg. OTP_SW3_VOLT = 0x60<BR />OK: write reg. OTP_SW3_PWRUP = 0x3d<BR />OK: write reg. OTP_SW3_CONFIG1 = 0x53<BR />OK: write reg. OTP_SW3_CONFIG2 = 0x3b<BR />OK: write reg. OTP_SW4_VOLT = 0xb1<BR />OK: write reg. OTP_SW4_PWRUP = 0x47<BR />OK: write reg. OTP_SW4_CONFIG1 = 0x53<BR />OK: write reg. OTP_SW4_CONFIG2 = 0x2b<BR />OK: write reg. OTP_SW5_VOLT = 0xb0<BR />OK: write reg. OTP_SW5_PWRUP = 0x51<BR />OK: write reg. OTP_SW5_CONFIG1 = 0x53<BR />OK: write reg. OTP_SW5_CONFIG2 = 0x33<BR />OK: write reg. OTP_SW6_VOLT = 0x38<BR />OK: write reg. OTP_SW6_PWRUP = 0x51<BR />OK: write reg. OTP_SW6_CONFIG1 = 0x53<BR />OK: write reg. OTP_SW6_CONFIG2 = 0x13<BR />OK: write reg. OTP_SW7_VOLT = 0x15<BR />OK: write reg. OTP_SW7_PWRUP = 0x47<BR />OK: write reg. OTP_SW7_CONFIG1 = 0x53<BR />OK: write reg. OTP_SW7_CONFIG2 = 0x03<BR />OK: write reg. OTP_LDO1_VOLT = 0x52<BR />OK: write reg. OTP_LDO1_PWRUP = 0x5b<BR />OK: write reg. OTP_LDO1_CONFIG = 0x06<BR />OK: write reg. OTP_LDO2_VOLT = 0x50<BR />OK: write reg. OTP_LDO2_PWRUP = 0x00<BR />OK: write reg. OTP_LDO2_CONFIG = 0x12<BR />OK: write reg. OTP_LDO3_VOLT = 0x52<BR />OK: write reg. OTP_LDO3_PWRUP = 0x65<BR />OK: write reg. OTP_LDO3_CONFIG = 0x06<BR />OK: write reg. OTP_LDO4_VOLT = 0x52<BR />OK: write reg. OTP_LDO4_PWRUP = 0x6f<BR />OK: write reg. OTP_LDO4_CONFIG = 0x06<BR />OK: write reg. OTP_VSNVS_CONFIG = 0x00<BR />OK: write reg. OTP_OV_BYPASS1 = 0x7f<BR />OK: write reg. OTP_OV_BYPASS2 = 0x0f<BR />OK: write reg. OTP_UV_BYPASS1 = 0x7f<BR />OK: write reg. OTP_UV_BYPASS2 = 0x0f<BR />OK: write reg. OTP_ILIM_BYPASS1 = 0x7f<BR />OK: write reg. OTP_ILIM_BYPASS2 = 0x0f<BR />OK: write reg. OTP_PROG_IDH = 0x00<BR />OK: write reg. OTP_PROG_IDL = 0x00<BR />OK: write reg. OTP_DEBUG1 = 0x01<BR />OK: write reg. OTP_SW_COMP1 = 0x00<BR />OK: write reg. OTP_SW_COMP2 = 0x00<BR />OK: write reg. OTP_SW_COMP3 = 0x00<BR />OK: write reg. FCMD = 0xa5<BR />OK: write reg. FCMD = 0xa4<BR />OK: write reg. TEST_FLAGS = 0x07<BR />OK: set TBBEN digital pin = LOW<BR />OK: set PWRON digital pin = HIGH</P><P>&nbsp;</P><P>&nbsp;</P><P>&nbsp;</P> Tue, 27 Jun 2023 01:23:03 GMT https://community.nxp.com/t5/Power-Management/KITPF8200FRDPGM-error/m-p/1676441#M2761 jjaa 2023-06-27T01:23:03Z https://community.nxp.com/t5/Power-Management/KITPF8200FRDPGM-error/m-p/1676460#M2763 <P>Please review attached manual for your issue：</P> Tue, 27 Jun 2023 02:20:46 GMT https://community.nxp.com/t5/Power-Management/KITPF8200FRDPGM-error/m-p/1676460#M2763 guoweisun 2023-06-27T02:20:46Z