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    <title>topic [FS45] Question about fault detection and DFS. in Power Management</title>
    <link>https://community.nxp.com/t5/Power-Management/FS45-Question-about-fault-detection-and-DFS/m-p/1665110#M2698</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I was hoping someone can verify/clarify some passages from the datasheet (Rev. 7).&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Passage&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;12.3: When DFS enabled, the FS state machine monitors and counts faults happening.&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Question&lt;/STRONG&gt;&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;If DFS is disabled, does the FS state machine&amp;nbsp;&lt;EM&gt;not&lt;/EM&gt; monitor and count faults happening? FLT_ERR_CNT never increments?&lt;/LI&gt;&lt;LI&gt;In that case, is it correct to assume that the intermediate value impact will never trigger?&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Passage&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;12.5.3: The fault error counter is incremented by 1, each time RSTB and/or FS0B pin is asserted. When FS0B is asserted, the fault error counter is incremented by 1, every time the watchdog error counter maximum value is reached.&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Question&lt;/STRONG&gt;&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;If RSTB and/or FS0B is asserted through SPI request, does it still count towards FLT_ERR_CNT, or only when RSTB/FS0B is asserted as part of a fault impact?&lt;/LI&gt;&lt;LI&gt;If a fault occurs (e.g. V&lt;FONT size="1 2 3 4 5 6 7"&gt;CORE&lt;/FONT&gt; undervoltage) but is configured to have no impact on FS0B or RSTB (e.g. V&lt;FONT size="1 2 3 4 5 6 7"&gt;CORE&lt;/FONT&gt; is not safety critical) am I correct to assume it will &lt;STRONG&gt;not&lt;/STRONG&gt; increment FLT_ERR_CNT? E.g. the selected impact on safety outputs FS0B and RSTB determines if it will increment the fault counter?&lt;/LI&gt;&lt;LI&gt;Same question but regarding specifically the second half of the passage: If FS0B is not asserted when the watchdog error counter maximum value is reached, it doesn't increment FLT_ERR_CNT? SO also for the watchdog, the impact defines FLT_ERR_CNT behaviour?&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;&lt;STRONG&gt;Passage&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;12.7.1.6 and 12.7.2.4: The overvoltage detection switches off the regulator.&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Question&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;Regarding the disabling of the regulator; is it permanently switched off, until the next Wake-up or POR?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I hope I have understood these passages correctly, but I would like to verify.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Kind regards,&lt;/P&gt;&lt;P&gt;Joey&lt;/P&gt;</description>
    <pubDate>Wed, 07 Jun 2023 13:48:38 GMT</pubDate>
    <dc:creator>Joey_van_Hummel</dc:creator>
    <dc:date>2023-06-07T13:48:38Z</dc:date>
    <item>
      <title>[FS45] Question about fault detection and DFS.</title>
      <link>https://community.nxp.com/t5/Power-Management/FS45-Question-about-fault-detection-and-DFS/m-p/1665110#M2698</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I was hoping someone can verify/clarify some passages from the datasheet (Rev. 7).&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Passage&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;12.3: When DFS enabled, the FS state machine monitors and counts faults happening.&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Question&lt;/STRONG&gt;&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;If DFS is disabled, does the FS state machine&amp;nbsp;&lt;EM&gt;not&lt;/EM&gt; monitor and count faults happening? FLT_ERR_CNT never increments?&lt;/LI&gt;&lt;LI&gt;In that case, is it correct to assume that the intermediate value impact will never trigger?&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Passage&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;12.5.3: The fault error counter is incremented by 1, each time RSTB and/or FS0B pin is asserted. When FS0B is asserted, the fault error counter is incremented by 1, every time the watchdog error counter maximum value is reached.&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Question&lt;/STRONG&gt;&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;If RSTB and/or FS0B is asserted through SPI request, does it still count towards FLT_ERR_CNT, or only when RSTB/FS0B is asserted as part of a fault impact?&lt;/LI&gt;&lt;LI&gt;If a fault occurs (e.g. V&lt;FONT size="1 2 3 4 5 6 7"&gt;CORE&lt;/FONT&gt; undervoltage) but is configured to have no impact on FS0B or RSTB (e.g. V&lt;FONT size="1 2 3 4 5 6 7"&gt;CORE&lt;/FONT&gt; is not safety critical) am I correct to assume it will &lt;STRONG&gt;not&lt;/STRONG&gt; increment FLT_ERR_CNT? E.g. the selected impact on safety outputs FS0B and RSTB determines if it will increment the fault counter?&lt;/LI&gt;&lt;LI&gt;Same question but regarding specifically the second half of the passage: If FS0B is not asserted when the watchdog error counter maximum value is reached, it doesn't increment FLT_ERR_CNT? SO also for the watchdog, the impact defines FLT_ERR_CNT behaviour?&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;&lt;STRONG&gt;Passage&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;12.7.1.6 and 12.7.2.4: The overvoltage detection switches off the regulator.&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Question&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;Regarding the disabling of the regulator; is it permanently switched off, until the next Wake-up or POR?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I hope I have understood these passages correctly, but I would like to verify.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Kind regards,&lt;/P&gt;&lt;P&gt;Joey&lt;/P&gt;</description>
      <pubDate>Wed, 07 Jun 2023 13:48:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Power-Management/FS45-Question-about-fault-detection-and-DFS/m-p/1665110#M2698</guid>
      <dc:creator>Joey_van_Hummel</dc:creator>
      <dc:date>2023-06-07T13:48:38Z</dc:date>
    </item>
    <item>
      <title>Re: [FS45] Question about fault detection and DFS.</title>
      <link>https://community.nxp.com/t5/Power-Management/FS45-Question-about-fault-detection-and-DFS/m-p/1665255#M2699</link>
      <description>&lt;P&gt;Hi Joey,&lt;/P&gt;
&lt;P&gt;A1. No, the fail-safe state machine&amp;nbsp;still monitors, counts&amp;nbsp;faults and FLT_ERR_CNT increases as normal, but the deep fail-safe mode is not entered when the fault error counter reaches max value.&lt;/P&gt;
&lt;P&gt;A2.&amp;nbsp;No, intermediate will trigger as it configured.&lt;/P&gt;
&lt;P&gt;B1. Yes, SPI request will not increase FLT ERR Counter and only fault impact.&lt;/P&gt;
&lt;P&gt;B2. Yes, your understanding is correct.&lt;/P&gt;
&lt;P&gt;B3. Yes, you are right.&lt;/P&gt;
&lt;P&gt;C. Yes.&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Tomas&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Tomas&lt;/P&gt;</description>
      <pubDate>Wed, 07 Jun 2023 14:29:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Power-Management/FS45-Question-about-fault-detection-and-DFS/m-p/1665255#M2699</guid>
      <dc:creator>TomasVaverka</dc:creator>
      <dc:date>2023-06-07T14:29:06Z</dc:date>
    </item>
    <item>
      <title>Re: [FS45] Question about fault detection and DFS.</title>
      <link>https://community.nxp.com/t5/Power-Management/FS45-Question-about-fault-detection-and-DFS/m-p/1665268#M2700</link>
      <description>Hi Tomas,&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;Thanks for the confirmation, it's much appreciated.&lt;BR /&gt;&lt;BR /&gt;Kind regards,&lt;BR /&gt;Joey</description>
      <pubDate>Wed, 07 Jun 2023 14:43:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Power-Management/FS45-Question-about-fault-detection-and-DFS/m-p/1665268#M2700</guid>
      <dc:creator>Joey_van_Hummel</dc:creator>
      <dc:date>2023-06-07T14:43:34Z</dc:date>
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