topic Re: PF3000 LDOG in Power Management

PF3000 LDOG

timvielhaber — Mon, 18 Mar 2019 12:06:13 GMT

I have a 5V implementation with the PF3000 PMIC. I previously used the chip on a different design but with 4V input. Now with 5V input, I am using an external FET and LDO controller to generate the VIN from my 5V. I am getting only 2.8v on VIN. It appears if the LDOG gate signal is also at 5V, so FET is not ON? Is there any setup of the PF3000 that needs to be done to enable the LDO circuit to generate the proper gate signal to the external FET? Any other ideas why I have no FET gate drive?

Re: PF3000 LDOG

guoweisun — Mon, 18 Mar 2019 12:37:08 GMT

Do you mind to show your schematic?

Re: PF3000 LDOG

timvielhaber — Thu, 21 Mar 2019 12:00:58 GMT

The STANDBY line has been tied to GND, but device continues to be in STANDBY. Also, the rechargeable battery has been removed and replaced with a 3V input, generated from the VPWR 5V rail with a resistive voltage divider.

The PF3000 was pre-programmed prior to board assembly with the following configuration file using the KITPF3000FRDMPGM board:

DEVICE:PF3000
ADDR:E0:DATA:04 // OTP_SYS_PWRON_CFG|OTP_SYS_DVS_CLK|OTP_SYS_SEQ_CLK
ADDR:E8:DATA:00 // OTP_SYS_PGOOD
ADDR:FF:DATA:08 // OTP_SYS_I2C_DEVICE_ADDRESS
NSUP01:SW1A
ADDR:A0:DATA:1B // SW1A VOUT
ADDR:A1:DATA:02 // SW1A SEQ
ADDR:A2:DATA:0D // SW1A CFG
NSUP02:SW1B
ADDR:A8:DATA:1B // SW1B VOUT
ADDR:A9:DATA:02 // SW1B SEQ
NSUP03:SW2
ADDR:AC:DATA:0F // SW2 VOUT
ADDR:AD:DATA:04 // SW2 SEQ
ADDR:AE:DATA:01 // SW2 CFG
NSUP04:SW3
ADDR:B0:DATA:09 // SW3 VOUT
ADDR:B1:DATA:03 // SW3 SEQ
ADDR:B2:DATA:01 // SW3 CFG
NSUP05:SWBST
ADDR:BC:DATA:00 // SWBST VOUT
ADDR:BD:DATA:06 // SWBST SEQ
NSUP06:VSNVS
ADDR:C0:DATA:06 // VSNVS VOUT
NSUP07:VLDO1
ADDR:C8:DATA:0F // VLDO1 VOUT
ADDR:C9:DATA:04 // VLDO1 SEQ
NSUP08:VLDO2
ADDR:CC:DATA:08 // VLDO2 VOUT
ADDR:CD:DATA:04 // VLDO2 SEQ
NSUP09:VCC_SD
ADDR:D0:DATA:03 // VCC_SD VOUT
ADDR:D1:DATA:05 // VCC_SD SEQ
NSUP10:V33
ADDR:D4:DATA:01 // V33 VOUT
ADDR:D5:DATA:01 // V33 SEQ
NSUP11:VLDO3
ADDR:D8:DATA:07 // VLDO3 VOUT
ADDR:D9:DATA:04 // VLDO3 SEQ
NSUP12:VLDO4
ADDR:DC:DATA:00 // VLDO4 VOUT
ADDR:DD:DATA:04 // VLDO4 SEQ

Re: PF3000 LDOG

guoweisun — Fri, 22 Mar 2019 03:18:52 GMT

1: For more Standby mode setting details information refer to datasheet page55/95.

2: Remove battery and also remove 3V resistors divider on VPWR to try.

Re: PF3000 LDOG

timvielhaber — Fri, 22 Mar 2019 18:48:26 GMT

I believe the device is stuck in STANDBY. The STANDBY pin is tied low via a wire jumper between pin 4 and 5 of the PF3000 (pin 5 is the ICTEST pin). I pre-programmed the PF3000, but there is no OTP setting for the STANDBYINV bit, so qith STANDBY tied low, the device should NOT be in STANDBY. It appears the STBY_LOWPOWER_B is not really applicable.

The 3V resistor divider was provided as an input to the LICELL pin in stead of the battery. I have tried this with a battery, open circuit, or tied to 3V on the LICELL input.

VPWR is tied to the 5V rail.

Re: PF3000 LDOG

guoweisun — Tue, 26 Mar 2019 07:40:35 GMT

What are you set about STANDBYINV and STBY_LOWPOWER_B in your application?

If you don't know you can try to read them out by IIC?

Re: PF3000 LDOG

arinfrolova1990 — Mon, 15 Jul 2019 05:17:25 GMT

Usually I never comment on blogs but your article is so convincing that I never stop myself to say something about it. You’re doing a great job Man,Keep it up.