topic Re: PF3000 front-end input LDO regulator issue in Power Management

PF3000 front-end input LDO regulator issue

prezek — Wed, 23 Feb 2022 13:53:53 GMT

We have some issue with PMIC PF3000. It appears only occasionally, but it is a big issue for us. If it happens, we are not able to get out of the error state.

The issue:

5V is provided to pin VPWR, but VIN genertes only 1.5V - 1.8V

I think the problem is caused by not activating external PMOS pass FET MP1. (see attached Figure 3)

Additional info:

Figures form startup sequence:

Yellow - VPWR

Light blue - VIN

Purple - LDOG

Figure 1: Correct startup waveforms (the purple signal is partly hidden by the yellow one)

Figure 2: Failure startup waveforms (the purple signal is hidden by the yellow one)

Figure 3: Detail on failure startup waveforms

Voltage measured on PMIC pins:

1	INTB	0.3V
2	SD_VSEL	0V
3	RESETBMCU	0V
4	STANDBY	0V
5	ICTEST	0V
6	SW1AFB	0.3V
7	SW1AIN	1.5V
8	SW1ALX	0.3V
9	SW1BLX	0.011V
10	SW1BIN	1.5V
11	SW1BFB	0.011V
12	GNDREF1	0V
13	VLDO1IN	1.5V
14	VLDO1	0.54V
15	VLDO2	0.11V - 0.44V
16	VLDO2IN	0V
17	SW2LX	0V
18	SW2IN	1.5V
19	SW2FB	0V
20	VLDO3	0.024V
21	VLDO34IN	1.5V
22	VLDO4	0.02V
23	VHALF	0V
24	VINREFDDR	0V
25	VREFDDR	0V
26	GNDREF2	0V
27	SW3FB	0V
28	SW3IN	1.5V
29	SW3LX	0V
30	LDOG	4.97V
31	VPWR	4.98V
32	V33	0V
33	VCC_SD	0V
34	VSNVS	0.68V
35	SWBSTLX	1.5V
36	LICELL	1.17V
37	SWBSTFB	1.2V
38	VIN2	1.5V
39	VDDOTP	0V
40	GNDREF	0V
41	VCORE	0V
42	VIN	1.5V
43	VCOREDIG	0.94V
44	VCOREREF	1.08V
45	SDA	0.3V
46	SCL	0.3V
47	VDDIO	0.3V
48	PWRON	2.75V

Re: PF3000 front-end input LDO regulator issue

JozefKozon — Thu, 24 Feb 2022 14:11:34 GMT

Hello Petr,

what PFET have you used? Please refer to section 4 in the AN5161. FDMA908PZ is recommended to be used. I would also like to point you to AN5094 Layout guidelines. Both application notes can be downloaded from this link.

With Best Regards,
Jozef

Re: PF3000 front-end input LDO regulator issue

prezek — Fri, 25 Feb 2022 10:21:56 GMT

Hello Jozef,

thank you for your reply.

We are using PFET PMPB15XP (it's recommended by the datasheet).

I don't think that the transistor could cause the issue. If you look on the waveforms, you can see, that PMIC doesn't try to open the gate of the transistor.

Figure 4: schematics of our circuit

Re: PF3000 front-end input LDO regulator issue

JozefKozon — Fri, 25 Feb 2022 12:42:31 GMT

Hello Petr,

thank you for the PFET confirmation and for the schematic. I have found a thread where a customer had a similar issue. The reason was another load connected to the VIN pin. But I see from the schematic, that you haven't anything other connected to the VIN pin. I have posted the description of your issue to our application team. As soon as I will receive an answer, I will definitely reply to you.

With Best Regards,

Jozef

Re: PF3000 front-end input LDO regulator issue

JozefKozon — Wed, 02 Mar 2022 06:30:53 GMT

Hello Petr,

there is still no answer from the application team. As soon as I will receive one I will definitely reply to you.

Thank you for your patience.

With Best Regards,

Jozef

Re: PF3000 front-end input LDO regulator issue

JozefKozon — Fri, 04 Mar 2022 06:28:25 GMT

Hello Petr,

I have just received an answer from the application engineer. He asks me to confirm with you, that there is no other load connected to the VIN pin. Although from your schematic I see, that there is no other load connected, could you please confirm it?

With Best Regards,

Jozef

Re: PF3000 front-end input LDO regulator issue

prezek — Fri, 04 Mar 2022 07:35:06 GMT

Hi Jozef,

I confirm that we are not using the VIN net for anything else then suppling the PF3000. Everything connected to the signal is showed on the schematic above.

I have tried 2 things if the error state could be forced by increasing load on VIN:

I have tried adding additional capacitor between VIN and GND – I didn’t see any difference

I have tried adding resistor load between VIN and GND:

- with 1 k there was no difference

- with 100 ohm additional load there VIN signal was not stable until the external FET was activated

I was not able to increase occurrence of the error state by additional load

I would like to ask you how the start of using the external FET is timed. It looks like it takes approx. 400ms. Is the timing block supplied from VIN or VPWR?

Could you share any details about generating VIN before external FET is activated? (current limitation, timing, reference sources etc.)

Thank you, Petr

Re: PF3000 front-end input LDO regulator issue

JozefKozon — Wed, 09 Mar 2022 07:46:12 GMT

Hi Petr,

I have posted your confirmation to the application engineer, but I haven't received an answer from him yet. I have added another application engineer in the communication loop. As soon as I will receive an answer from either of them, I will definitely reply to you.

Thank you for your patience.

With Best Regards,

Jozef

Re: PF3000 front-end input LDO regulator issue

JozefKozon — Thu, 10 Mar 2022 06:56:08 GMT

Hi Petr,

the added application engineer has just answered me. He requests to measure the VPWR current when the fault happens.

DESCRIPTION

Its hard to say what’s going on. Could there be a current limit at the VIN node?

When in this problem state, what is the current drawn from VPWR?

With Best Regards,

Jozef

Re: PF3000 front-end input LDO regulator issue

prezek — Thu, 10 Mar 2022 14:29:30 GMT

Hi Jozef,

we have installed a current probe to the device.

It measures current drawn from VPWR and charging current of filtering capacitors. We are not able to separate the capacitors from VPWR.

Yellow - current

Green - VPWR (partially hidden by LDOG)

Blue - VIN

Ping -LDOG

Figure 5: Correct startup waveform

Figure 6: Faulty state startup waveform

Figure 7: Detail on faulty startup waveform

I have one potentially useful information:

When we disconnect power supply, the voltage on VIN falls very slowly (because of the capacitors) and if we reconnect power supply, the PMIC stays in the error state. The voltage can fall bellow 0.4 V and it stays in error state (tens of seconds without power supply).

Figure 8: Power supply disabled for 22s, VIN drops to 0.23 V, PMIC stays in error state

When we disconnect power supply for longer time, PMIC usually starts correctly.

Is the PMIC internally powered from VIN or some other pin? I could measure voltage on any pin...

Re: PF3000 front-end input LDO regulator issue

JozefKozon — Tue, 15 Mar 2022 06:12:31 GMT

Hi Petr,

please see below an answer from the application engineer with a suggestion.

DESCRIPTION

I am not sure if the PMIC is getting stuck in some weird state due to startup from a non-discharged VPWR. Is it possible to add a small bleeder resistor from VPWR to ground to allow it to discharge faster, and see if the problem resolves?

With Best Regards,

Jozef

Re: PF3000 front-end input LDO regulator issue

prezek — Tue, 15 Mar 2022 11:49:32 GMT

Hi Jozef,

I have induced the issue and then I have tried 2 experiments and added 100 ohm resistor in 2 places:

1. Between VPWR and GND

2. Between VIN and GND

Then I disconnected power supply. In both cases the corresponding voltage dropped very quickly below 1mV. After reconnecting power supply the error state continued in both cases.

Discharging resistor on VPWR or VIN dos not help.

Could you please tell me which pin is supplying the logic, timing, etc. of driving LDOG and internal states?

Re: PF3000 front-end input LDO regulator issue

JozefKozon — Wed, 16 Mar 2022 09:46:30 GMT

Hi Petr,

please send the board for debugging to the application engineer. I will pass the application engineer's details to in the ticket. Please see the application engineer's reply below.

DESCRIPTION

I believe there is a path from VPWR that powers logic, bandgap etc.

I think best may be to send a board to Bruce in TJN for debug.

With Best Regards,

Jozef

Re: PF3000 front-end input LDO regulator issue

prezek — Tue, 19 Apr 2022 16:28:35 GMT

Hi Jozef,

I tried to create a tool for simple enforcing the issue for you. I noticed that the issue occurs when I power up the PMIC, then unplug the power for approx. 10 minutes and then re-enable power.

I measured which voltage is discharged so slowly and found out that SWBSTFB has 0.2 V 10 minutes after disconnecting the power.

Then I found out that I can force the error state by charging capacitors connected to SWBSTFB to 0.25 V before connecting the PMIC to the power supply.

After we added 1 k resistor parallel to the capacitors on SWBSTFB signal, the issue never occurred.

I don`t see any reason for this behaviour in the datasheet of PF3000.

Can you please confirm that 0.2 V on SWBSTFB can be the cause of the error and explain it?

Will there be any revision with correction of this issue?

Thank you, Petr

Re: PF3000 front-end input LDO regulator issue

JozefKozon — Fri, 22 Apr 2022 06:08:00 GMT

Hi Petr,

I have received an answer from the application engineer. He tried to reproduce the issue on our PF3000EVB, but there wasn't voltage on the SWBSTFB as in your case. It looks like in the case of our PF3000EVB, the energy is dissipated, but in case of your board, the energy stays accumulated in the capacitor. I have checked your schematic and its correct. Please check an AN5094 attached and please follow the layout recommendations. You can also refer to the Gerber files of the KITPF3000FRDMEVM.zip attached. Please consider purchase the KITPF3000FRDMEVM and FRDM-KL25Z for evaluation.

With Best Regards,

Jozef