Power ManagementのトピックRe: SBC 6513CAE

Re: SBC 6513CAE

qiaoqin_wang — Fri, 18 Jun 2021 06:42:46 GMT

ok, i got it,thanks.

but i also have a confusion about the MCFS6513CAE debug pin how to configure the debug mode,

if the debug pin need to pull up 10K to Vpre and pull down to GND?

another question is how to exit the debug mode?

Re: SBC 6513CAE

naveenm — Fri, 18 Jun 2021 12:05:14 GMT

Hi, This message has been moved from SafeAssure Community. This is the link for original message. Can somebody please attend to this query?

SBC 6513CAE - NXP Community

Regards,

NaveenM

Re: SBC 6513CAE

r40959 — Fri, 18 Jun 2021 13:06:34 GMT

Hello In case you don’t have it already, please download our AN5238 ‘FS6500 and FS4500 Safe System Basis Chip Hardware Design and Product Guidelines’. This user guide will help you a lot with detailed guidelines. Debug pin voltage must be between 2.8V and 4.35V when device powers up: Below recommended HW connection from AN5238 p.28 (5.8 FS6500 and FS4500 Debug pin): • DBG_COUT = 10 to 22nF • DBG_RPD = 11kΩ • DBG_RPU = 10kΩ both are necessary Debug mode is detected at ‘FS select pin config’ phase during power up sequence (Figure 53. Start-up scheme in datasheet). If debug pin voltage changes after this phase, it will not impact debug mode entry/exit. To exit debug mode, debug pin voltage must be < 2.1V before powering up again the device. we hope it helps best regards

Re: SBC 6513CAE

guoweisun — Mon, 21 Jun 2021 01:45:42 GMT

Are you clear with your questions? if not please let me know!