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    <title>topic Re: PF5200 TBBEN mode in Power Management</title>
    <link>https://community.nxp.com/t5/Power-Management/PF5200-TBBEN-mode/m-p/1265149#M1448</link>
    <description>&lt;P&gt;Hi&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Why don't use NXP GUI to do that OTP? you also don't use the OTP programmer board to do it, right?&lt;/P&gt;</description>
    <pubDate>Tue, 20 Apr 2021 12:49:09 GMT</pubDate>
    <dc:creator>guoweisun</dc:creator>
    <dc:date>2021-04-20T12:49:09Z</dc:date>
    <item>
      <title>PF5200 TBBEN mode</title>
      <link>https://community.nxp.com/t5/Power-Management/PF5200-TBBEN-mode/m-p/1264543#M1443</link>
      <description>&lt;P&gt;I need to program the PMIC PF5024(EVAL board) without using NXP GUI.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;The procedure mentioned for TBBEN mode :&lt;/P&gt;&lt;DIV&gt;&lt;UL&gt;&lt;LI&gt;J34 switch to be between 2-3 (Shorted to Ground)&lt;/LI&gt;&lt;LI&gt;J40 between 2-3 it has to be high&lt;/LI&gt;&lt;LI&gt;j39 between 1-2 (gnd)&lt;/LI&gt;&lt;LI&gt;Configure the register values&lt;/LI&gt;&lt;LI&gt;Connect the J40 between 1-2, so it will be tied to Ground&lt;/LI&gt;&lt;LI&gt;Now the values should be configured&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;How we tried to achieve above sequence :&lt;/P&gt;&lt;DIV&gt;&lt;UL&gt;&lt;LI&gt;J34 switch to be between 2-3 (Shorted to Ground)&lt;/LI&gt;&lt;LI&gt;J40 kept open and Pin2 of J40 Tied to a 1.5V power supply&lt;/LI&gt;&lt;LI&gt;j39 between 1-2 (gnd)&lt;/LI&gt;&lt;LI&gt;Configure the register values&lt;UL&gt;&lt;LI&gt;(When I tried reading back the OTP registers , it reads back zero always.)&lt;/LI&gt;&lt;/UL&gt;&lt;/LI&gt;&lt;LI&gt;J40 kept open and&amp;nbsp;Pin2 of J40 Tied to&amp;nbsp; GND (We done this via a 1K resistance)&lt;/LI&gt;&lt;LI&gt;After this we didn't see any change in BUCK voltages&lt;UL&gt;&lt;LI&gt;(The I2C read fails and it returns NACK always )&lt;/LI&gt;&lt;/UL&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;So I need know how to verify following steps:&lt;/P&gt;&lt;P&gt;1. Read back OTP registers writes in TBBEN mode&lt;BR /&gt;2. Is there any sequence missing to perform TBB mode?&lt;BR /&gt;&lt;BR /&gt;Any help will be appreciated.&lt;BR /&gt;&lt;BR /&gt;Thanks.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Tue, 20 Apr 2021 05:14:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Power-Management/PF5200-TBBEN-mode/m-p/1264543#M1443</guid>
      <dc:creator>satheesh_mb</dc:creator>
      <dc:date>2021-04-20T05:14:45Z</dc:date>
    </item>
    <item>
      <title>Re: PF5200 TBBEN mode</title>
      <link>https://community.nxp.com/t5/Power-Management/PF5200-TBBEN-mode/m-p/1265149#M1448</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Why don't use NXP GUI to do that OTP? you also don't use the OTP programmer board to do it, right?&lt;/P&gt;</description>
      <pubDate>Tue, 20 Apr 2021 12:49:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Power-Management/PF5200-TBBEN-mode/m-p/1265149#M1448</guid>
      <dc:creator>guoweisun</dc:creator>
      <dc:date>2021-04-20T12:49:09Z</dc:date>
    </item>
    <item>
      <title>Re: PF5200 TBBEN mode</title>
      <link>https://community.nxp.com/t5/Power-Management/PF5200-TBBEN-mode/m-p/1265214#M1449</link>
      <description>&lt;P&gt;1. The NXP GUI supports only Windows OS and I like to use Linux system for configuring the PMIC's. Having Linux helps more in automation so I can avoid the manual selection from GUI.&lt;/P&gt;&lt;P&gt;2. Yes. The OTP programmer board wasn't used. I have an FTDI device and using it to communicate with PMIC.&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;Also , Is there any reference document&amp;nbsp; available for&amp;nbsp; configuring the PMIC without GUI and OTP programmer board ?&lt;/P&gt;</description>
      <pubDate>Tue, 20 Apr 2021 13:58:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Power-Management/PF5200-TBBEN-mode/m-p/1265214#M1449</guid>
      <dc:creator>satheesh_mb</dc:creator>
      <dc:date>2021-04-20T13:58:17Z</dc:date>
    </item>
    <item>
      <title>Re: PF5200 TBBEN mode</title>
      <link>https://community.nxp.com/t5/Power-Management/PF5200-TBBEN-mode/m-p/1265810#M1457</link>
      <description>&lt;P&gt;There is no too much resource to support your own OTP software and programmer board.&lt;/P&gt;
&lt;P&gt;For the less number&amp;nbsp; parts' OTP you can select NXP official OTP programmer board and GUI tool.&lt;/P&gt;
&lt;P&gt;For the mass products, you can contact with local NXP or NXP distributors to do OTP after IC assembly during manufacture.&lt;/P&gt;</description>
      <pubDate>Wed, 21 Apr 2021 11:18:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Power-Management/PF5200-TBBEN-mode/m-p/1265810#M1457</guid>
      <dc:creator>guoweisun</dc:creator>
      <dc:date>2021-04-21T11:18:23Z</dc:date>
    </item>
    <item>
      <title>Re: PF5200 TBBEN mode</title>
      <link>https://community.nxp.com/t5/Power-Management/PF5200-TBBEN-mode/m-p/1265897#M1458</link>
      <description>&lt;P&gt;Thanks &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/138749"&gt;@guoweisun&lt;/a&gt; for the response.&lt;BR /&gt;&lt;BR /&gt;One more point to clarify regarding the TBB mode,&lt;BR /&gt;&lt;BR /&gt;On some PMIC I do see a &lt;STRONG&gt;Test mode Entry key write&amp;nbsp;&lt;/STRONG&gt;to enable&amp;nbsp; the debug mode.&lt;BR /&gt;IS there any sequence is need for PF5024? If yes can we get those info's.&lt;BR /&gt;&lt;BR /&gt;Thanks,&lt;/P&gt;</description>
      <pubDate>Wed, 21 Apr 2021 14:07:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Power-Management/PF5200-TBBEN-mode/m-p/1265897#M1458</guid>
      <dc:creator>satheesh_mb</dc:creator>
      <dc:date>2021-04-21T14:07:02Z</dc:date>
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