topic Re: linker ram config strangeness in MQX Software Solutions

linker ram config strangeness

billnd — Fri, 04 Oct 2013 13:12:16 GMT

Why do many (maybe all) of the supplied linker files set the end of ram 0xf lower than the last physical ram location. Example time...

This linker definition...

define symbol __ICFEDIT_region_RAM_start__ = 0x1fff0000;

define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFF0;

...is from the twrk53n512 bsp. Clearly stating that the last address of ram should be 0x2000FFF0. However in the device, the last actual ram address is 0x2000FFFF.

Does anyone know why its done like this?

Thanks in advance,

BillND

Re: linker ram config strangeness

c0170 — Mon, 07 Oct 2013 05:45:32 GMT

Hello BillND,

according to The Procedure Call Standard for the ARM Architecture (AAPCS), stack should be 8 byte aligned (this can be set in Cortex M4 to either 4byte aligned or 8byte aligned - ARM Information Center). MQX linkers define it as 4byte aligned. Therefore the RAM end address has 0 (last 4 bytes).

A link on KEIL website, you can find more information also in the document for AAPCS, which is available online

Compiler User Guide: Compiler eight-byte alignment features

Regards,

0xc0170