MQX Priorities and H/W Interrupt conflicts - Kinetis

Cdn_aye — Sat, 17 Jun 2017 16:45:44 GMT

I have a scheduling / kernal problem with tasks and interrupts.... I think. I see at infrequent times that I can't reproduce failures in services and I think the IRQ and Task priorities are wrong. I am using MQX 4.1 on a MK20dx256VLL10 core.

I found a place in the code where the NVIC priorities are not using the CMSIS calls

NVICIP62 = (uint8_t)DEF_SPEED_RECAL_PRIORITY_FTM0; // NVICIP62: PRI62=0xB0, change FTM0 interrupt priority to 11, below USB task priority

also this is defined here

_bsp_int_init ((IRQInterruptIndex)INT_FTM0, 4, 0, TRUE); // sets priority of interrupts, loads vector table

and then the task using the results of the data collected above

{ge_SERVER_TSK, server_task, 2400, 9, "server_tsk", 0, 0L, 0},

I think these priorities are not correct set. I know that 0 - 7 are for the kernal so the task is ok, but setting the hardware in two places and one being an odd number doesn't seem correct (but I am not sure given the understanding I have of using odd priorities for H/W and even for Tasks in MQX, however does this apply when the CMSIS calls are bypassed as above)? Can anyone advise me please on the best method?

Should I just remove the NVICIP62 register setting, since the mqx/cmsis call is setting the priority, and is this a good priority for a timer task that should run in the background but not override other irq's? I know it is all design dependent, but what I am asking is whether there is an obvious error in the above code. I have read through all the posts on the irq task priorities and still find the whole mqx, bsp shifting this... and that... and offsetting ... confusing.

Thanks for any advice.

Robert

Re: MQX Priorities and H/W Interrupt conflicts - Kinetis

danielchen — Tue, 20 Jun 2017 07:18:34 GMT

Hi Robert:

I didn't find your code snippet in Freescale released MQX 4.1 source package, where did you get this source or you modified based on MQX 4.1?

On cortex-M4 core based platforms, the MQX RTOS interrupt processing is designed this way. Kinetis K family MCUs support 16 hardware interrupt priority levels. Internally MQX RTOS maps even levels (0, 2, 4, ... 14 ) for MQX RTOS applications while odd levels (1, 3, ..., 15) are used internally. MQX RTOS application interrupt levels are 0 to 7, the mapping from MQX RTOS application levels 0 to 7 to hardware priority (0, 2, to 14) is implemented in the _bsp_int_init () function.

Regards

Daniel

MQX Software SolutionsのトピックRe: MQX Priorities and H/W Interrupt conflicts - Kinetis

MQX Priorities and H/W Interrupt conflicts - Kinetis

Re: MQX Priorities and H/W Interrupt conflicts - Kinetis