MQX Software SolutionsのトピックRe: Re: Floating point using generate _int_kernel_isr() ??

Floating point using generate _int_kernel_isr() ??

arnogir — Mon, 20 Apr 2015 14:44:13 GMT

Hello

I'm using a tower K60n512 with MQX 4.1.1 with KDS 2.0.0

I have the following configuration:

1) In Settings/Target Procession/ Float ABI = FP instruction

2) In Settings/Target Procession/ FPU Type=fpv4-sp-d16

3)in user_config.h:

#define MQXCFG_ENABLE_FP 1
#define MQX_INCLUDE_FLOATING_POINT_IO 1

4) In setings\Cross ARM C Compiler\Preprocessor:

"_AEABI_LC_CTYPE=C"

"__VFPV4__=1"

"__STRICT_ANSI__=1"

"_DEBUG=1"

In a Main task, I made following:

 test1 = 16.365;
 test2 = test1 * 2;

So when I do a Step on line2, execution stop on an ISR (Refer to joined file)

Do you have any idea why this crash?

NB: I had a similar project bu with the Tower K70 without any crash on float calculs:smileyplain:

Re: Floating point using generate _int_kernel_isr() ??

arnogir — Wed, 22 Apr 2015 13:05:07 GMT

No body has some idea?

:smileyblush:

Re: Floating point using generate _int_kernel_isr() ??

egoodii — Wed, 22 Apr 2015 13:09:43 GMT

This has been covered -- FP must be enabled in the CPU by your direct control.

Re: Floating point using generate _int_kernel_isr() ??

arnogir — Wed, 22 Apr 2015 13:17:25 GMT

Hello

I seen some thing to do this, but not on a K60. Then, could you indicate to me how activate FP on CPU K60?

And then why this not needed on a K70?

:smileyhappy:

Re: Floating point using generate _int_kernel_isr() ??

egoodii — Wed, 22 Apr 2015 13:25:16 GMT

I was TRYING to get you to do a little of your own legwork. A simple search of 'K60 floating point enable' gave a list, about the fourth of which is:

Re: Using Cortex-M4 Single Precision Floating point unit

Re: Re: Floating point using generate _int_kernel_isr() ??

arnogir — Wed, 22 Apr 2015 13:44:31 GMT

I have already found some part of code to "enable" explicitly the FPU:

; CPACR is located at address 0xE000ED88
LDR.W R0, =0xE000ED88
; Read CPACR
LDR R1, [R0]
; Set bits 20-23 to enable CP10 and CP11 coprocessors
ORR R1, R1, #(0xF << 20)
; Write back the modified value to the CPACR
STR R1, [R0]

But I don't found any explanation of this register in the RM.

I use MQX: this is not done by an OS services?

And then, why this work without any add with Tower K70?

I will test this code...

I add and call this code before float manipulation:


void vPortEnableVFP(void) 
 {
 
 /* The FPU enable bits are in the CPACR. */
 __asm volatile (
 " ldr.w r0, =0xE000ED88 \n" /* CAPCR, 0xE000ED88 */
 " ldr r1, [r0] \n" /* read CAPR */
 " orr r1, r1, #(0xf<<20) \n" /* Enable CP10 and CP11 coprocessors */
 " str r1,[r0] \n" /* store to new value back */
 : /* no output */
 : /* no input */
 : "r0","r1" /* clobber */
 );

But this not work again.:smileyconfused:

Re: Re: Floating point using generate _int_kernel_isr() ??

arnogir — Wed, 22 Apr 2015 13:54:39 GMT

Note: I use Tower K60 - KDS v2.0.0 - MQX 4.1.1

Re: Floating point using generate _int_kernel_isr() ??

egoodii — Wed, 22 Apr 2015 16:37:20 GMT

It is not in the RM because Freescale doesn't document ANYTHING that is 'core' to ARM. For ANYTHING that is 'basic' to the architecture, you must go to the ARM website.

Re: Floating point using generate _int_kernel_isr() ??

arnogir — Thu, 23 Apr 2015 05:21:15 GMT

Ok,

I understand this.

But for my problem, adding lines written above don't solve my problem:smileyplain:.

And then why all work on a K70 without these line, and an equivalent project not work on K60?:smileyconfused:

Re: Re: Floating point using generate _int_kernel_isr() ??

arnogir — Thu, 23 Apr 2015 06:14:14 GMT

MQX has a file named "not.s in \mqx\source\psp\cortex_m\core\M4\boot.s with following code:

#if MQXCFG_ENABLE_FP && PSP_HAS_FPU
 /* CPACR is located at address 0xE000ED88 */
 LDR.W R0, =0xE000ED88
 /* Read CPACR */
 LDR R1, [R0]
 /* Set bits 20-23 to enable CP10 and CP11 coprocessors */
 ORR R1, R1, #(0xF << 20)
 /* Write back the modified value to the CPACR */
 STR R1, [R0]
 /* turn off fpu register stacking in exception entry */
 
 ldr r0, =0xE000EF34 /* FPCCR */
 mov r1, #0
 str r1, [r0]
 #endif

But never execute this code.

I will check if the define ENABLE_FP and PSP_HAS_FPU are defined, but nothing line code of boot.s file are executed.

How activate this part?

Edit:

According file mqx\source\psp\cortex_m\kinetis.h, the CPU defined for the Tower K60 is (in user_config.h)MQX_CPU = BSP_CPU_MK60DN512Z

So with this CPU, the #define PSP_HAS_FPU is not define. THen I deduce my processor does not have FPU?

This will explain why this work with the K70 and not with my K60.

How know which CPU has oar hasn't FPU?

Re: Floating point using generate _int_kernel_isr() ??

RadekS — Thu, 23 Apr 2015 16:09:32 GMT

Yes, you are right.

Your MCU has no FPU unit.

We support three different K60 twr boards and only one has FPU unit.

I suppose that you have old TWR-K60N512 or new TWR-K60D100 board. These boards are assembled by MK60N512 (old name) or MK60DN512(new name) chips.

TWR-K60F120M is assembled by MK60FN1M which contains FPU unit (“F” in part name). Chips with "D" in part name has no FPU unit.

I hope it helps you.

Have a great day,
RadekS

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