topic Re: Is it possible to enable or disable DDR while running the code in K70? in MQX Software Solutions

Is it possible to enable or disable DDR while running the code in K70?

pramodk_g_ — Tue, 17 Jun 2014 16:38:39 GMT

Hi everyone,

I am working on K70 with MQX 4.0 on a TWR module. In my project I want to store my high frequency acquisition data to RAM for fast processing. Since there is not enough space in SRAM I planned to use DDR memory while acquisition and processing. All the other times I want to disable DDR to reduce the power conception. Is it possible to enable or disable DDR dynamically in MQX ? . One thing I noticed that RAM selection is done before building our project. Is it possible to use internal SRAM always and enable DDR when necessary?

Thanks,

Pramod.

Re: Is it possible to enable or disable DDR while running the code in K70?

Carlos_Musich — Thu, 19 Jun 2014 01:29:14 GMT

In a MQX project you can choose different Build Configurations.In the case of K70 you can find SRAM_Data and DDR_Data configurations. This means that the linker file is configured to store your data in SRAM or DDR. In this case data means variables.

If you have huge buffers where you store the aquired data you cans select SRAM_DATA and edit the linker file to allocate another buffer in external DDR. If you are using CodeWarrior this files is located in
C:\Freescale\Freescale_MQX_4_1\mqx\source\bsp\twrk70f120m\gcc_cw

Please note that all the future K70 projects will be affected by this modification. Alternately you can save a copy of this file in your project's path and configure the porject to use the copy of the file. If you are using CodeWarrior you can do this in menu Project > Properties > C/C++ Build > Settings > Linker > Input

If you are not using variables and you are just writing raw data in DDR you can simply enable DDR and read/write directly the memory address you want. In this case you dont need to edit the linker file.

In init_hw.c which is located in C:\Freescale\Freescale_MQX_4_1\mqx\source\bsp\twrk70f120m you will find DDR2 initialization.

/* Initialize SDRAM */
// _bsp_ddr2_setup();

Finally, if you want to disable or enable DDR you can unclock this module using bit 14 of SIM_SCGC3 register.

Hope this helps.

Best regards,
Carlos

Re: Is it possible to enable or disable DDR while running the code in K70?

pramodk_g_ — Thu, 19 Jun 2014 07:22:23 GMT

Hi ,

Thanks Carlos_Musich for your valuable feed back. I think I would go this option :

store the aquired data you cans select SRAM_DATA and edit the linker file to allocate another buffer in external DDR. Also I plan to disable the DDR clock after its usage and re enable it necessary, so that i can reduce the power conception. As you said i have opened intflash_sramdata.ld file located in C:\Freescale\Freescale_MQX_4_1\mqx\source\bsp\twrk70f120m\gcc_cw and don't know how I can allocate another buffer in external DDR. Can please explain how to do this linker file.

Thanks and have a good day,

Pramod.

Re: Is it possible to enable or disable DDR while running the code in K70?

Carlos_Musich — Fri, 20 Jun 2014 00:49:19 GMT

Hi Paramod,

This is not fast to explain, the document I attached in MQX memory usage will be very helpful to understand how to manipulate the linker file. Please see chapter 4.5 which explains how to relocate a function in external RAM, you can do the same with variables and arrays.

Best regards,

Carlos

MQX memory usage

Re: Is it possible to enable or disable DDR while running the code in K70?

pramodk_g_ — Mon, 23 Jun 2014 16:49:45 GMT

Hi Carlos_Musich,

i have gone through the document you are given, it was really helpful. But I am using freescale compiler tools not gcc, so I think i have to modify .lcf rather than .ld file. Is that correct?. I also tried with modifying .lcf file ,but am getting an error like "Linker command file error at line 137 Section not found: .main_application_bss" . I have attached the modified .lcf file , please let me know where i am wrong.

MEMORY

{

vectorrom (RX): ORIGIN = 0x00000000, LENGTH = 0x00000400

cfmprotrom (R): ORIGIN = 0x00000400, LENGTH = 0x00000020

rom (RX): ORIGIN = 0x00000420, LENGTH = 0x000FFBE0 # Code + Const data

ram (RW): ORIGIN = 0x1FFF0000, LENGTH = 0x00020000 # SRAM - RW data

myram (RW): ORIGIN = 0x70000000, LENGTH = 0x08000000 # DDR2 - RW data

# kernel space starts after RAM variables (Location of MQX Kernel data + MQX heap)

end_of_kd (RW): ORIGIN = 0x2000FFF0, LENGTH = 0x00000000

# Boot stack reused by MQX Kernel data

bstack (RW): ORIGIN = 0x2000FA00, LENGTH = 0x00000200 # Boot stack

end_bstack (RW): ORIGIN = 0x2000FC00, LENGTH = 0x00000000

}

KEEP_SECTION { .vectors_rom, .vectors_ram, .cfmconfig }

SECTIONS

{

__INTERNAL_SRAM_BASE = 0x1FFF0000;

__INTERNAL_SRAM_SIZE = 0x00020000;

# This symbol is unused in SRAM target (runtime check ensure that SRAM pool = Kernel pool),

# it is defined here just to keep linker quiete

__SRAM_POOL = 0x2000FFF0;

__INTERNAL_FLASH_BASE = 0x00000000;

__INTERNAL_FLASH_SIZE = 0x00100000;

__INTERNAL_FLEXNVM_BASE = 0;

__INTERNAL_FLEXNVM_SIZE = 0;

__UNCACHED_DATA_END = 0x2000FFF0;

__EXTERNAL_MRAM_BASE = 0x60000000;

__EXTERNAL_MRAM_SIZE = 0x00080000;

__EXTERNAL_MRAM_ROM_BASE = 0x60000000;

__EXTERNAL_MRAM_ROM_SIZE = 0x00000000;

__EXTERNAL_MRAM_RAM_BASE = 0x60000000;

__EXTERNAL_MRAM_RAM_SIZE = 0x00080000;

__EXTERNAL_DDR2_RAM_BASE = 0x70000000;

__EXTERNAL_DDR2_RAM_SIZE = 0x08000000;

__EXTERNAL_LCD_BASE = 0x60000000;

__EXTERNAL_LCD_SIZE = 0x1FFFF;

__EXTERNAL_LCD_DC_BASE = 0x60010000;

# MQX link time configurations

__DEFAULT_PROCESSOR_NUMBER = 1;

__DEFAULT_INTERRUPT_STACK_SIZE = 1024;

__KERNEL_DATA_VERIFY_ENABLE = 0; # Test SDRAM read/write

# Flashx configurations

__FLASHX_SECT_SIZE = 0x1000;

.vectors :

{

__VECTOR_TABLE_ROM_START = .; # Runtime vector table in sram

*(.vectors_rom)

. = ALIGN (0x4);

} > vectorrom

.cfmprotect :

{

*(.cfmconfig)

. = ALIGN (0x4);

} > cfmprotrom

.main_application :

{

*(KERNEL)

*(S_BOOT)

*(IPSUM)

*(.text)

*(.init)

*(.fini)

*(.eini)

*(.ctors)

*(.dtors)

. = ALIGN(0x4);

*(.rodata)

. = ALIGN(0x4);

*(.rdata)

. = ALIGN(0x4);

*(.exception)

. = ALIGN(0x4);

__exception_table_start__ = .;

EXCEPTION

__exception_table_end__ = .;

__sinit__ = .;

STATICINIT

. = ALIGN(0x4);

__COPY_OF_DATA = .;

} > rom

.main_application_data : AT(__COPY_OF_DATA)

{

. = ALIGN(128);

__VECTOR_TABLE_RAM_START = .; # Runtime vector table in sram

*(.vectors_ram)

. = ALIGN(512);

__BDT_BASE = .;

*(.usb_bdt)

__BDT_END = .;

__START_DATA = .;

*(.data)

__END_DATA = .;

. = ALIGN(0x4);

__START_SDATA = .;

*(.sdata)

__END_SDATA = .;

. = ALIGN(0x4);

__SDA_BASE = .;

__SDA_BASE_ = __SDA_BASE;

. = ALIGN(16);

} > ram

___CodeStart = __COPY_OF_DATA + SIZEOF(.main_application_data);

.my_ram : AT(___CodeStart)

{

. = ALIGN (0x4);

___myRAMStart = .;

*(.myCodeInRAM)

___myRAMEnd = .;

. = ALIGN (0x4);

} > myram

___CodeSize = ___myRAMEnd - ___myRAMStart

.main_application_bss :

{

. = ALIGN(0x10);

__START_SBSS = .;

*(.sbss)

*(SCOMMON)

__END_SBSS = .;

__START_BSS = .;

*(.bss)

*(COMMON)

__END_BSS = .;

. = ALIGN(16);

__UNCACHED_DATA_START = .;

} >> ram

.kernel_data : #AT(ADDR(.main_application_bss) + SIZEOF(.main_application_bss))

{

__KERNEL_DATA_START = ALIGN(0x10);

}

.end_of_kernel_data :

{

__KERNEL_DATA_END = .;

} > end_of_kd

.boot_stack :

{

_stack_end = .;

} > bstack

.end_of_boot_stack :

{

_stack_addr = .;

__SP_INIT = .;

__BOOT_STACK_ADDRESS = .;

} > end_bstack

# Locate the ROM copy table into ROM after the initialized data

_romp_at = __COPY_OF_DATA + SIZEOF(.main_application_data) + SIZEOF(.my_ram);

.romp : AT (_romp_at)

{

__S_romp = _romp_at;

WRITEW(__COPY_OF_DATA); #ROM start address

WRITEW(ADDR(.main_application_data)); #RAM start address

WRITEW(SIZEOF(.main_application_data)); #size

WRITEW(0);

}

_flashx_start = __COPY_OF_DATA + SIZEOF(.main_application_data) + SIZEOF(.romp);

# flashx working area spans across the whole rest of Flash memory

__FLASHX_START_ADDR = ((_flashx_start + __FLASHX_SECT_SIZE - 1) / __FLASHX_SECT_SIZE) * __FLASHX_SECT_SIZE;

__FLASHX_END_ADDR = __INTERNAL_FLASH_BASE + __INTERNAL_FLASH_SIZE;

}

/* EOF */

Thanks,

Pramod

Re: Is it possible to enable or disable DDR while running the code in K70?

Carlos_Musich — Tue, 24 Jun 2014 00:42:56 GMT

Hi Paramod,

As you said you are using Freescale compiler you must modify .lcf and the sintax in source files changes:

#pragma define_section mySectionInRAM “.myCodeInRAM” far_absolute RX

__declspec(mySectionInRAM) void funcInROM(int flag)

Regarding to the linker error:

You are locating the code below between to sections located in ram segment. .main_application_data : AT(__COPY_OF_DATA) opens ram segment ( } > ram ) and .main_application_bss : append in ram segment ( } >> ram). Please put the code below BEFORE .main_application_data : AT(__COPY_OF_DATA).

___CodeStart = __COPY_OF_DATA + SIZEOF(.main_application_data);

.my_ram : AT(___CodeStart)

{

. = ALIGN (0x4);

___myRAMStart = .;

*(.myCodeInRAM)

___myRAMEnd = .;

. = ALIGN (0x4);

} > myram

___CodeSize = ___myRAMEnd - ___myRAMStart

regards,

Carlos

Re: Is it possible to enable or disable DDR while running the code in K70?

pramodk_g_ — Tue, 24 Jun 2014 16:23:52 GMT

Thanks Carlos_Musich,

I solved that building error and it was due to a syntax error. Now I can compile the code. But when I have look at the .MAP file i couldn't see anything on the new ram section. Also I found that ___CodeStart, ___CodeSize etc are zero. So nothing is copied into my_ram segment. I have attached my code and .lcf file , please let me know where i am went wrong.

Thanks

Pramod.

****************************************************************************

extern unsigned long ___CodeStart[];

#define CodeStart (unsigned long)___CodeStart

extern unsigned long ___CodeSize[];

#define CodeSize (unsigned long)___CodeSize

extern unsigned long ___myRAMStart[];

#define StartAddr (unsigned long)___myRAMStart

uint_8 *Source; /* use this pointer to get the begining of the Code */

uint_8 *Destiny; /* use this pointer to get the RAM destination address */

uint_32 MemorySize; /* Gets the size of the code that is being copied */

void copyToMyRAM(void);//Function prototype

calling this function from main program

void copyToMyRAM(void)

{

/* Initialize the pointers to start the copy from Flash to RAM */

Source = (unsigned char *)(CodeStart);

Destiny = (unsigned char *)(StartAddr);

MemorySize = (unsigned long)(CodeSize);

/* Copying the code from Flash to RAM */

while(MemorySize--)

{

*Destiny++ = *Source++;

}

#pragma define_section mySectionInRAM ".myCodeInRAM" far_abs RW

#pragma section mySectionInRAM begin

struct {

uint_16 data0[3000];

uint_16 data1[3000];

uint_16 data2[3000];

uint_16 data3[3000];

uint_16 data4[3000];

uint_16 data5[3000];

uint_16 data6[3000];

uint_16 data7[3000];

} CTMData; // = { 0x82, 0x65, 0x77, 0x32, 0x84, 0x69, 0x83, 0x84 };

void funcInROM(int flag);

void funcInROM(int flag){

if (flag > 0)

{

printf("Option 1 selected \n\r");

printf("Executing funcInROM() = %c \n\r", CTMData.data1);

printf("This function is executed from section myROM \n\r");

}

#pragma section mySectionInRAM end

****************************************************************************

MEMORY

{

vectorrom (RX): ORIGIN = 0x00000000, LENGTH = 0x00000400

cfmprotrom (R): ORIGIN = 0x00000400, LENGTH = 0x00000020

rom (RX): ORIGIN = 0x00000420, LENGTH = 0x000FFBE0 # Code + Const data

ram (RW): ORIGIN = 0x1FFF0000, LENGTH = 0x00020000 # SRAM - RW data

myram (RW): ORIGIN = 0x70000000, LENGTH = 0x08000000 # DDR2 - RW data

# kernel space starts after RAM variables (Location of MQX Kernel data + MQX heap)

end_of_kd (RW): ORIGIN = 0x2000FFF0, LENGTH = 0x00000000

# Boot stack reused by MQX Kernel data

bstack (RW): ORIGIN = 0x2000FA00, LENGTH = 0x00000200 # Boot stack

end_bstack (RW): ORIGIN = 0x2000FC00, LENGTH = 0x00000000

}

KEEP_SECTION { .vectors_rom, .vectors_ram, .cfmconfig }

SECTIONS

{

__INTERNAL_SRAM_BASE = 0x1FFF0000;

__INTERNAL_SRAM_SIZE = 0x00020000;

# This symbol is unused in SRAM target (runtime check ensure that SRAM pool = Kernel pool),

# it is defined here just to keep linker quiete

__SRAM_POOL = 0x2000FFF0;

__INTERNAL_FLASH_BASE = 0x00000000;

__INTERNAL_FLASH_SIZE = 0x00100000;

__INTERNAL_FLEXNVM_BASE = 0;

__INTERNAL_FLEXNVM_SIZE = 0;

__UNCACHED_DATA_END = 0x2000FFF0;

__EXTERNAL_MRAM_BASE = 0x60000000;

__EXTERNAL_MRAM_SIZE = 0x00080000;

__EXTERNAL_MRAM_ROM_BASE = 0x60000000;

__EXTERNAL_MRAM_ROM_SIZE = 0x00000000;

__EXTERNAL_MRAM_RAM_BASE = 0x60000000;

__EXTERNAL_MRAM_RAM_SIZE = 0x00080000;

__EXTERNAL_DDR2_RAM_BASE = 0x70000000;

__EXTERNAL_DDR2_RAM_SIZE = 0x08000000;

__EXTERNAL_LCD_BASE = 0x60000000;

__EXTERNAL_LCD_SIZE = 0x1FFFF;

__EXTERNAL_LCD_DC_BASE = 0x60010000;

# MQX link time configurations

__DEFAULT_PROCESSOR_NUMBER = 1;

__DEFAULT_INTERRUPT_STACK_SIZE = 1024;

__KERNEL_DATA_VERIFY_ENABLE = 0; # Test SDRAM read/write

# Flashx configurations

__FLASHX_SECT_SIZE = 0x1000;

.vectors :

{

__VECTOR_TABLE_ROM_START = .; # Runtime vector table in sram

*(.vectors_rom)

. = ALIGN (0x4);

} > vectorrom

.cfmprotect :

{

*(.cfmconfig)

. = ALIGN (0x4);

} > cfmprotrom

.main_application :

{

*(KERNEL)

*(S_BOOT)

*(IPSUM)

*(.text)

*(.init)

*(.fini)

*(.eini)

*(.ctors)

*(.dtors)

. = ALIGN(0x4);

*(.rodata)

. = ALIGN(0x4);

*(.rdata)

. = ALIGN(0x4);

*(.exception)

. = ALIGN(0x4);

__exception_table_start__ = .;

EXCEPTION

__exception_table_end__ = .;

__sinit__ = .;

STATICINIT

. = ALIGN(0x4);

__COPY_OF_DATA = .;

} > rom

.main_application_data : AT(__COPY_OF_DATA )

{

. = ALIGN(128);

__VECTOR_TABLE_RAM_START = .; # Runtime vector table in sram

*(.vectors_ram)

. = ALIGN(512);

__BDT_BASE = .;

*(.usb_bdt)

__BDT_END = .;

__START_DATA = .;

*(.data)

__END_DATA = .;

. = ALIGN(0x4);

__START_SDATA = .;

*(.sdata)

__END_SDATA = .;

. = ALIGN(0x4);

__SDA_BASE = .;

__SDA_BASE_ = __SDA_BASE;

. = ALIGN(16);

} > ram

___CodeStart = __COPY_OF_DATA + SIZEOF(.main_application_data);

.my_ram : AT(___CodeStart)

{

. = ALIGN (0x4);

___myRAMStart = .;

*(.myCodeInRAM)

___myRAMEnd = .;

. = ALIGN (0x4);

} > myram

___CodeSize = ___myRAMEnd - ___myRAMStart;

.main_application_bss :

{

. = ALIGN(0x10);

__START_SBSS = .;

*(.sbss)

*(SCOMMON)

__END_SBSS = .;

__START_BSS = .;

*(.bss)

*(COMMON)

__END_BSS = .;

. = ALIGN(16);

__UNCACHED_DATA_START = .;

} >> ram

.kernel_data : #AT(ADDR(.main_application_bss) + SIZEOF(.main_application_bss))

{

__KERNEL_DATA_START = ALIGN(0x10);

}

.end_of_kernel_data :

{

__KERNEL_DATA_END = .;

} > end_of_kd

.boot_stack :

{

_stack_end = .;

} > bstack

.end_of_boot_stack :

{

_stack_addr = .;

__SP_INIT = .;

__BOOT_STACK_ADDRESS = .;

} > end_bstack

# Locate the ROM copy table into ROM after the initialized data

_romp_at = __COPY_OF_DATA + SIZEOF(.main_application_data) + SIZEOF(.my_ram);

.romp : AT (_romp_at)

{

__S_romp = _romp_at;

WRITEW(__COPY_OF_DATA); #ROM start address

WRITEW(ADDR(.main_application_data)); #RAM start address

WRITEW(SIZEOF(.main_application_data)); #size

WRITEW(0);

}

_flashx_start = __COPY_OF_DATA + SIZEOF(.main_application_data) + SIZEOF(.romp);

# flashx working area spans across the whole rest of Flash memory

__FLASHX_START_ADDR = ((_flashx_start + __FLASHX_SECT_SIZE - 1) / __FLASHX_SECT_SIZE) * __FLASHX_SECT_SIZE;

__FLASHX_END_ADDR = __INTERNAL_FLASH_BASE + __INTERNAL_FLASH_SIZE;

}

/* EOF */

Re: Is it possible to enable or disable DDR while running the code in K70?

Carlos_Musich — Wed, 25 Jun 2014 00:54:46 GMT

Hi Paramod,

would you submit a Service Request at www.freescale.com/support and attach your project to check it on our side? You can ask to assign the request to Carlos Musich :smileyhappy:

Regards,

Carlos