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    <title>MCX MicrocontrollersのトピックRe: MCXA265VPN Layout Suggestion</title>
    <link>https://community.nxp.com/t5/MCX-Microcontrollers/MCXA265VPN-Layout-Suggestion/m-p/2395964#M5645</link>
    <description>&lt;P&gt;Team,&lt;/P&gt;&lt;P&gt;Do you have a demo board with suggested routing? I need to know:&lt;/P&gt;&lt;P&gt;Trace widths sizes used to route between BGA pins?&lt;/P&gt;&lt;P&gt;Via types used and pad sizes with hole size?&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;thru hole, bbvia, stacked?&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;Spacings used between pins after routing?&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;DESCRIPTION = MCXA265VPN, NXP SEMICONDUCTORS&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;MXCA_169_BGA169 (10 mil pads with 19.7 mil pitch between pins)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thank you very much. for your support.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Dan Rogers&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Thu, 16 Jul 2026 11:35:12 GMT</pubDate>
    <dc:creator>DanRogers</dc:creator>
    <dc:date>2026-07-16T11:35:12Z</dc:date>
    <item>
      <title>MCXA265VPN Layout Suggestion</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/MCXA265VPN-Layout-Suggestion/m-p/2387350#M5580</link>
      <description>&lt;P&gt;NXP Team,&lt;/P&gt;&lt;P&gt;Do you have a&amp;nbsp;MCXA265VPN fanout example?&amp;nbsp; Need recommended via pad and hole size.&amp;nbsp; Are the vias in pads or between pins?&amp;nbsp; Need to have a solid GND plane under BGA?&lt;/P&gt;&lt;P&gt;Please help.&lt;/P&gt;&lt;P&gt;Thanks Dan Rogers&lt;/P&gt;</description>
      <pubDate>Sat, 27 Jun 2026 12:37:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/MCXA265VPN-Layout-Suggestion/m-p/2387350#M5580</guid>
      <dc:creator>DanRogers</dc:creator>
      <dc:date>2026-06-27T12:37:16Z</dc:date>
    </item>
    <item>
      <title>Re: MCXA265VPN Layout Suggestion</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/MCXA265VPN-Layout-Suggestion/m-p/2387370#M5581</link>
      <description>&lt;P&gt;&lt;A href="https://www.nxp.com.cn/docs/en/application-note/AN10778.pdf" target="_blank"&gt;AN10778 PCB layout guidelines for NXP MCUs in BGA packages&lt;/A&gt;&lt;/P&gt;</description>
      <pubDate>Sun, 28 Jun 2026 07:53:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/MCXA265VPN-Layout-Suggestion/m-p/2387370#M5581</guid>
      <dc:creator>db16122</dc:creator>
      <dc:date>2026-06-28T07:53:30Z</dc:date>
    </item>
    <item>
      <title>Re: MCXA265VPN Layout Suggestion</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/MCXA265VPN-Layout-Suggestion/m-p/2395964#M5645</link>
      <description>&lt;P&gt;Team,&lt;/P&gt;&lt;P&gt;Do you have a demo board with suggested routing? I need to know:&lt;/P&gt;&lt;P&gt;Trace widths sizes used to route between BGA pins?&lt;/P&gt;&lt;P&gt;Via types used and pad sizes with hole size?&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;thru hole, bbvia, stacked?&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;Spacings used between pins after routing?&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;DESCRIPTION = MCXA265VPN, NXP SEMICONDUCTORS&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;MXCA_169_BGA169 (10 mil pads with 19.7 mil pitch between pins)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thank you very much. for your support.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Dan Rogers&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 16 Jul 2026 11:35:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/MCXA265VPN-Layout-Suggestion/m-p/2395964#M5645</guid>
      <dc:creator>DanRogers</dc:creator>
      <dc:date>2026-07-16T11:35:12Z</dc:date>
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