topic 2S TDM Master: Persistent 1-slot downward shift during continuous DMA streaming in MCX Microcontrollers https://community.nxp.com/t5/MCX-Microcontrollers/2S-TDM-Master-Persistent-1-slot-downward-shift-during-continuous/m-p/2373820#M5458 <H3>1. Test Configuration</H3><UL><LI><DIV class="">I2S configured as <STRONG>TDM Master</STRONG>, DSP mode with short WS</DIV></LI><LI><DIV class=""><STRONG>8 slots per frame</STRONG>, 32-bit per slot, frame length = 256 bit</DIV></LI><LI><DIV class="">Using <STRONG>fsl_i2s_dma</STRONG> driver</DIV></LI><LI><DIV class=""><STRONG>Dual-buffer ping-pong</STRONG> transfer</DIV></LI><LI><DIV class="">FreeRTOS task waits on a semaphore from the DMA callback, fills the buffer, then calls I2S_TxTransferSendDMA to re-submit</DIV></LI><LI><DIV class="">Test data pattern: fixed 0x000Axxxx (upper 16 bits = 0x000A, lower 16 bits contain slot index and sample sequence number)</DIV></LI></UL><H3>2. Persistent One-Slot Downward Shift (100% Reproducible)</H3><DIV class="">Logic analyzer captures show:</DIV><UL><LI><DIV class="">Transmitted data is <STRONG>consistently shifted down by exactly one slot</STRONG></DIV></LI><LI><DIV class="">Data intended for <STRONG>Slot 0</STRONG> appears in the physical <STRONG>Slot 1</STRONG> position</DIV></LI><LI><DIV class="">Data intended for <STRONG>Slot 1</STRONG> appears in the physical <STRONG>Slot 2</STRONG> position</DIV></LI><LI><DIV class="">By extension, data intended for <STRONG>Slot 7</STRONG> appears in <STRONG>Slot 0 of the next frame</STRONG> (or is lost)</DIV></LI><LI><DIV class="">This shift is <STRONG>stable</STRONG> after the stream starts; it does not drift further over time and remains a fixed 1-slot offset</DIV></LI></UL><H3>3. Startup Data Misalignment (Intermittent)</H3><DIV class="">The logic analyzer occasionally observes:</DIV><UL><LI><DIV class="">After the <STRONG>WS frame sync pulse</STRONG>, the <STRONG>DATA line remains at low level (all zeros)</STRONG> for a period</DIV></LI><LI><DIV class="">After a <STRONG>blank interval of 1~3 frames</STRONG>, valid test data suddenly appears</DIV></LI><LI><DIV class="">Once the blank interval ends, the data still exhibits the <STRONG><STRONG>1-slot offset described in item 2<BR /></STRONG></STRONG><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Xanderwangx_0-1780141578772.png" style="width: 400px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/387359i961FF6CD42CA85AD/image-size/medium?v=v2&amp;px=400" role="button" title="Xanderwangx_0-1780141578772.png" alt="Xanderwangx_0-1780141578772.png" /></span><P>&nbsp;</P></DIV></LI></UL> Sat, 30 May 2026 11:46:49 GMT Xanderwangx 2026-05-30T11:46:49Z 2S TDM Master: Persistent 1-slot downward shift during continuous DMA streaming https://community.nxp.com/t5/MCX-Microcontrollers/2S-TDM-Master-Persistent-1-slot-downward-shift-during-continuous/m-p/2373820#M5458 <H3>1. Test Configuration</H3><UL><LI><DIV class="">I2S configured as <STRONG>TDM Master</STRONG>, DSP mode with short WS</DIV></LI><LI><DIV class=""><STRONG>8 slots per frame</STRONG>, 32-bit per slot, frame length = 256 bit</DIV></LI><LI><DIV class="">Using <STRONG>fsl_i2s_dma</STRONG> driver</DIV></LI><LI><DIV class=""><STRONG>Dual-buffer ping-pong</STRONG> transfer</DIV></LI><LI><DIV class="">FreeRTOS task waits on a semaphore from the DMA callback, fills the buffer, then calls I2S_TxTransferSendDMA to re-submit</DIV></LI><LI><DIV class="">Test data pattern: fixed 0x000Axxxx (upper 16 bits = 0x000A, lower 16 bits contain slot index and sample sequence number)</DIV></LI></UL><H3>2. Persistent One-Slot Downward Shift (100% Reproducible)</H3><DIV class="">Logic analyzer captures show:</DIV><UL><LI><DIV class="">Transmitted data is <STRONG>consistently shifted down by exactly one slot</STRONG></DIV></LI><LI><DIV class="">Data intended for <STRONG>Slot 0</STRONG> appears in the physical <STRONG>Slot 1</STRONG> position</DIV></LI><LI><DIV class="">Data intended for <STRONG>Slot 1</STRONG> appears in the physical <STRONG>Slot 2</STRONG> position</DIV></LI><LI><DIV class="">By extension, data intended for <STRONG>Slot 7</STRONG> appears in <STRONG>Slot 0 of the next frame</STRONG> (or is lost)</DIV></LI><LI><DIV class="">This shift is <STRONG>stable</STRONG> after the stream starts; it does not drift further over time and remains a fixed 1-slot offset</DIV></LI></UL><H3>3. Startup Data Misalignment (Intermittent)</H3><DIV class="">The logic analyzer occasionally observes:</DIV><UL><LI><DIV class="">After the <STRONG>WS frame sync pulse</STRONG>, the <STRONG>DATA line remains at low level (all zeros)</STRONG> for a period</DIV></LI><LI><DIV class="">After a <STRONG>blank interval of 1~3 frames</STRONG>, valid test data suddenly appears</DIV></LI><LI><DIV class="">Once the blank interval ends, the data still exhibits the <STRONG><STRONG>1-slot offset described in item 2<BR /></STRONG></STRONG><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Xanderwangx_0-1780141578772.png" style="width: 400px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/387359i961FF6CD42CA85AD/image-size/medium?v=v2&amp;px=400" role="button" title="Xanderwangx_0-1780141578772.png" alt="Xanderwangx_0-1780141578772.png" /></span><P>&nbsp;</P></DIV></LI></UL> Sat, 30 May 2026 11:46:49 GMT https://community.nxp.com/t5/MCX-Microcontrollers/2S-TDM-Master-Persistent-1-slot-downward-shift-during-continuous/m-p/2373820#M5458 Xanderwangx 2026-05-30T11:46:49Z Re: 2S TDM Master: Persistent 1-slot downward shift during continuous DMA streaming https://community.nxp.com/t5/MCX-Microcontrollers/2S-TDM-Master-Persistent-1-slot-downward-shift-during-continuous/m-p/2374134#M5460 <P>Hello&nbsp;<a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/263296">@Xanderwangx</a>&nbsp;,</P> <DIV>Thank you for your post. Could you please let us know which NXP MCU you are using? Also, are you working with one of our evaluation boards or a custom board? Are you using the SDK example code, or is this based on your own implementation? If it is your own code, would you be able to share it with us for further analysis?</DIV> <DIV>BR</DIV> <DIV>Celeste</DIV> Mon, 01 Jun 2026 02:43:56 GMT https://community.nxp.com/t5/MCX-Microcontrollers/2S-TDM-Master-Persistent-1-slot-downward-shift-during-continuous/m-p/2374134#M5460 Celeste_Liu 2026-06-01T02:43:56Z