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  <channel>
    <title>topic Re: [MCXN947] SAI_RxSetConfig() clears RCR4.FCOMB for multi-channel RX — bug confirmation request in MCX Microcontrollers</title>
    <link>https://community.nxp.com/t5/MCX-Microcontrollers/MCXN947-SAI-RxSetConfig-clears-RCR4-FCOMB-for-multi-channel-RX/m-p/2371287#M5430</link>
    <description>&lt;P&gt;Hello&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/214870"&gt;@maohuynh&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;Thanks for your post.&amp;nbsp;I am currently investigating the issue you raised and will get back to you as soon as possible.&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Celeste&lt;/P&gt;</description>
    <pubDate>Tue, 26 May 2026 11:17:44 GMT</pubDate>
    <dc:creator>Celeste_Liu</dc:creator>
    <dc:date>2026-05-26T11:17:44Z</dc:date>
    <item>
      <title>[MCXN947] SAI_RxSetConfig() clears RCR4.FCOMB for multi-channel RX — bug confirmation request</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/MCXN947-SAI-RxSetConfig-clears-RCR4-FCOMB-for-multi-channel-RX/m-p/2369913#M5422</link>
      <description>&lt;DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;Dear NXP Support Team,&lt;/SPAN&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;SPAN&gt;I am writing to report a potential bug I found in the MCUXpresso SDK SAI driver (&lt;/SPAN&gt;&lt;SPAN&gt;`fsl_sai.c`&lt;/SPAN&gt;&lt;SPAN&gt;)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;while developing an &lt;/SPAN&gt;&lt;SPAN&gt;**Active Noise Cancellation (ANC)**&lt;/SPAN&gt;&lt;SPAN&gt; system on the &lt;/SPAN&gt;&lt;SPAN&gt;**FRDM-MCXN947**&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;evaluation board. I would appreciate your confirmation of whether this is a known issue&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;and whether a fix is planned.&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;H3&gt;Project Overview&lt;/H3&gt;&lt;P class=""&gt;I am building a real-time ANC system on FRDM-MCXN947 with the following audio hardware:&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;&lt;STRONG&gt;4× INMP441 MEMS microphones&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;— feedforward and error microphones for the FxLMS algorithm&lt;/LI&gt;&lt;LI&gt;&lt;STRONG&gt;2× MAX98357A I2S amplifiers&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;— anti-noise speaker output via SAI1 TXD0 (P3_20)&lt;/LI&gt;&lt;LI&gt;&lt;STRONG&gt;Dual-core split:&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;Core0 handles all I/O (SAI DMA, LCD, shell), Core1 runs the FxLMS&lt;BR /&gt;DSP algorithm. IPC via MCMGR mailbox, 16 ms frame rate (256 samples @ 16 kHz).&lt;/LI&gt;&lt;/UL&gt;&lt;P class=""&gt;The system requires capturing all 4 microphones simultaneously on every 16 ms frame.&lt;BR /&gt;Because MCXN947 provides&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;only one DMA request line&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;for SAI1 RX&lt;BR /&gt;(kDma0RequestMuxSai1Rx = 101U), FIFO combine mode (RCR4.FCOMB) is the only&lt;BR /&gt;SDK-supported path to receive from both RXD0 and RXD1 with a single DMA channel.&lt;/P&gt;&lt;H3&gt;Bug Found&lt;/H3&gt;&lt;P class=""&gt;&lt;STRONG&gt;SDK version:&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;MCUXpresso SDK (mcuxsdk-core, commit&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;0455af2)&lt;BR /&gt;&lt;STRONG&gt;Driver versions:&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;fsl_sai&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;v2.4.11 /&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;fsl_sai_edma&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;v2.7.4&lt;BR /&gt;&lt;STRONG&gt;File:&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;drivers/sai/fsl_sai.c&lt;/P&gt;&lt;H4&gt;The problem&lt;/H4&gt;&lt;P class=""&gt;SAI_RxSetConfig()&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;unconditionally clears&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;RCR4.FCOMB&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;whenever&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;channelNums &amp;gt; 1,&lt;BR /&gt;even when the caller explicitly set&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;fifoCombine = kSAI_RXFifoCombineModeEnabledOnRead.&lt;/P&gt;&lt;P class=""&gt;The call chain is:&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;&lt;P&gt;&lt;STRONG&gt;SAI_RxSetFifoConfig()&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;(fsl_sai.c lines 1103–1105) — correctly sets&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;RCR4.FCOMB&lt;BR /&gt;from&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;config-&amp;gt;fifoCombine:&lt;/P&gt;&lt;PRE&gt;rcr4 &amp;amp;= ~I2S_RCR4_FCOMB_MASK;
rcr4 |= I2S_RCR4_FCOMB(config-&amp;gt;fifoCombine);   // ← set correctly
base-&amp;gt;RCR4 = rcr4;&lt;/PRE&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P&gt;&lt;STRONG&gt;SAI_RxSetConfig()&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;(fsl_sai.c lines 1439–1444) — runs&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;after&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;step 1 and&lt;BR /&gt;unconditionally clears it:&lt;/P&gt;&lt;PRE&gt;/* make sure combine mode disabled while multipe channel is used */
if (config-&amp;gt;channelNums &amp;gt; 1U)
{
    base-&amp;gt;RCR4 &amp;amp;= ~I2S_RCR4_FCOMB_MASK;   // ← always clears, ignores fifoCombine
}&lt;/PRE&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P&gt;&lt;STRONG&gt;SAI_TransferRxSetConfigEDMA()&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;(fsl_sai_edma.c lines 362–368) — has an&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;assert()&lt;BR /&gt;that correctly&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;requires&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;fifoCombine&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;to be non-zero when&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;channelNums &amp;gt; 1, but it&lt;BR /&gt;validates the config struct, not the hardware register. The assert passes while&lt;BR /&gt;RCR4.FCOMB&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;is already 0 in the hardware.&lt;/P&gt;&lt;/LI&gt;&lt;/OL&gt;&lt;P class=""&gt;The comment at step 2 says&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;EM&gt;"make sure combine mode disabled while multiple channel is used"&lt;/EM&gt;&lt;BR /&gt;— this appears to be a copy of the TX-side logic incorrectly applied to RX. For RX, FIFO&lt;BR /&gt;combine mode is&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;required&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;for multi-channel DMA, as documented in the example code&lt;BR /&gt;in&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;fsl_sai_edma.c&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;lines 340–350.&lt;/P&gt;&lt;H4&gt;Observed symptom&lt;/H4&gt;&lt;P class=""&gt;After calling&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;SAI_TransferRxSetConfigEDMA()&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;with&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;channelMask = kSAI_Channel0Mask | kSAI_Channel1Mask&lt;BR /&gt;and&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;fifoCombine = kSAI_RXFifoCombineModeEnabledOnRead:&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;SAI1-&amp;gt;RCR4 &amp;amp; I2S_RCR4_FCOMB_MASK == 0&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;(should be 2)&lt;/LI&gt;&lt;LI&gt;SAI RX FIFO overflow errors fire immediately on&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;AUDIO_CaptureStart()&lt;/LI&gt;&lt;LI&gt;kStatus_SAI_RxError&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;callbacks flood the system (hundreds per second)&lt;/LI&gt;&lt;LI&gt;The FreeRTOS UART shell task (priority 2) becomes completely unresponsive&lt;/LI&gt;&lt;LI&gt;No valid audio data is received&lt;/LI&gt;&lt;/UL&gt;&lt;P class=""&gt;Reverting to single-channel (kSAI_Channel0Mask&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;only,&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;channelNums=1) restores&lt;BR /&gt;full system operation immediately.&lt;/P&gt;&lt;H4&gt;Secondary issue — confusing enum values&lt;/H4&gt;&lt;P&gt;The&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;_sai_fifo_combine&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;enum in&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;fsl_sai.h&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;(lines 272–277) uses swapped numeric values&lt;BR /&gt;for TX vs RX directions:&lt;/P&gt;&lt;PRE&gt;kSAI_FifoCombineModeEnabledOnRead      = 1U,  // TX only
kSAI_RXFifoCombineModeEnabledOnRead    = 2U,  // RX only&lt;/PRE&gt;&lt;P&gt;The example code in&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;fsl_sai_edma.c&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;line 348 uses&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;kSAI_FifoCombineModeEnabledOnRead&lt;BR /&gt;(the TX enum, value=1) for an RX configuration. On devices with&lt;BR /&gt;FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE=1&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;this silently configures write-combine instead&lt;BR /&gt;of read-combine for RX.&lt;/P&gt;&lt;HR /&gt;&lt;H3&gt;Current Workaround&lt;/H3&gt;&lt;P class=""&gt;I currently work around this by manually restoring&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;RCR4.FCOMB&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;after&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;SAI_TransferRxSetConfigEDMA()&lt;BR /&gt;returns:&lt;/P&gt;&lt;PRE&gt;SAI_TransferRxSetConfigEDMA(SAI1, &amp;amp;s_saiRxHandle, &amp;amp;rxConfig);

/* Workaround: fsl_sai.c:1443 clears RCR4.FCOMB unconditionally when channelNums&amp;gt;1 */
SAI1-&amp;gt;RCR4 = (SAI1-&amp;gt;RCR4 &amp;amp; ~I2S_RCR4_FCOMB_MASK) | I2S_RCR4_FCOMB(2U);&lt;/PRE&gt;&lt;P class=""&gt;This is fragile and requires direct register access bypassing the SDK API.&lt;/P&gt;&lt;H3&gt;Questions&lt;/H3&gt;&lt;OL&gt;&lt;LI&gt;Is this a confirmed bug in&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;fsl_sai&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;v2.4.11?&lt;/LI&gt;&lt;LI&gt;Is there a known fix or patched version available?&lt;/LI&gt;&lt;LI&gt;Is the example code at&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;fsl_sai_edma.c:348&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;(kSAI_FifoCombineModeEnabledOnRead&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;used&lt;BR /&gt;for RX) intentional or also a documentation error?&lt;/LI&gt;&lt;LI&gt;Is there an official supported way to capture from SAI1 RXD0 + RXD1 simultaneously&lt;BR /&gt;on MCXN947 using the public SDK API that I may have missed?&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;A full bug report with the complete call chain analysis is attached.&lt;/P&gt;&lt;P&gt;Thank you for your time and support.&lt;/P&gt;&lt;P class=""&gt;Best regards,&lt;BR /&gt;Huynh Mao&lt;BR /&gt;&lt;A href="mailto:huynhmaook@gmail.com" target="_blank" rel="noopener"&gt;huynhmaook@gmail.com&lt;/A&gt;&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Fri, 22 May 2026 03:58:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/MCXN947-SAI-RxSetConfig-clears-RCR4-FCOMB-for-multi-channel-RX/m-p/2369913#M5422</guid>
      <dc:creator>maohuynh</dc:creator>
      <dc:date>2026-05-22T03:58:30Z</dc:date>
    </item>
    <item>
      <title>Re: [MCXN947] SAI_RxSetConfig() clears RCR4.FCOMB for multi-channel RX — bug confirmation request</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/MCXN947-SAI-RxSetConfig-clears-RCR4-FCOMB-for-multi-channel-RX/m-p/2371287#M5430</link>
      <description>&lt;P&gt;Hello&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/214870"&gt;@maohuynh&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;Thanks for your post.&amp;nbsp;I am currently investigating the issue you raised and will get back to you as soon as possible.&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Celeste&lt;/P&gt;</description>
      <pubDate>Tue, 26 May 2026 11:17:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/MCXN947-SAI-RxSetConfig-clears-RCR4-FCOMB-for-multi-channel-RX/m-p/2371287#M5430</guid>
      <dc:creator>Celeste_Liu</dc:creator>
      <dc:date>2026-05-26T11:17:44Z</dc:date>
    </item>
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