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    <title>MCX MicrocontrollersのトピックMCXN947: How can the period of the PPS signal be controlled with the ADDEND register?</title>
    <link>https://community.nxp.com/t5/MCX-Microcontrollers/MCXN947-How-can-the-period-of-the-PPS-signal-be-controlled-with/m-p/2338292#M5079</link>
    <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;Reference is made to the “MCX N Reference Manual” Rev. 7.&lt;BR /&gt;The FRDM-MCX947 board with the NXP SDK v25.06.00 is used here.&lt;/P&gt;&lt;P&gt;The configuration for PTP looks like this:&lt;/P&gt;&lt;LI-CODE lang="c"&gt;#ifdef ENET_PTP1588FEATURE_REQUIRED
   enet_ptp_config_t ptpConfig;
   memset(&amp;amp;ptpConfig, 0x00, sizeof(ptpConfig));
   config.specialControl      = kENET_MulticastAllEnable | kENET_StoreAndForward;
   ptpConfig.fineUpdateEnable = true;  
   ptpConfig.ptp1588V2Enable  = true;
   ptpConfig.tsRollover       = kENET_DigitalRollover;
   config.ptpConfig           = &amp;amp;ptpConfig;
   config.ptpClkHz            = 50000000U;
#endif &lt;/LI-CODE&gt;&lt;P&gt;The digital rollover mode is used here. For the GPIO, PORT 3 pin 20 is used:&lt;/P&gt;&lt;LI-CODE lang="c"&gt;   CLOCK_EnableClock(kCLOCK_Port3);

   const port_pin_config_t pin_config = {
                                         kPORT_PullDisable,
                                         kPORT_LowPullResistor,
                                         kPORT_FastSlewRate,
                                         kPORT_PassiveFilterDisable,
                                         kPORT_OpenDrainDisable,
                                         kPORT_LowDriveStrength,
                                         kPORT_MuxAlt1,
                                         kPORT_InputBufferEnable,
                                         kPORT_InputNormal,
                                         kPORT_UnlockRegister};

   /* PORT3_20 is configured as TRIG_OUT0 */
   PORT_SetPinConfig(PORT3, 20U, &amp;amp;pin_config);

   CLOCK_EnableClock(kCLOCK_InputMux);
   INPUTMUX-&amp;gt;EXT_TRIG[0] = INPUTMUX_EXT_TRIGN_EXT_TRIG_INP(0x2F);&lt;/LI-CODE&gt;&lt;P&gt;In order to output a PPS signal at all, the TSCFUPDT bit and the ADDEND register must be set:&lt;/P&gt;&lt;LI-CODE lang="c"&gt;ENET0-&amp;gt;MAC_TIMESTAMP_CONTROL |= ENET_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK;
ENET_Ptp1588CorrectTimerInFine(ENET0, 0xFFFFFFFF);&lt;/LI-CODE&gt;&lt;P&gt;This now creates a PPS period of 1000 005 596ns. The clock runs too fast here. As PTP clock&amp;nbsp;50MHz is specified here, which leads to a MAC_SUB_SECOND_INCREMENT of 20.&lt;/P&gt;&lt;P&gt;If I have understood correctly, then the fine correction can be done via the ADDEND register.&amp;nbsp;The new ADDEND (Anew) is calculated as follows:&lt;/P&gt;&lt;P&gt;Anew = Aold * (Time wrong / 1e9)&lt;/P&gt;&lt;P&gt;In my case, this gives the following value:&lt;BR /&gt;&lt;BR /&gt;Anew = 0xFFFFFFFF * (1000005596 / 1e9) = 0x100005DE2&lt;/P&gt;&lt;P&gt;The new value cannot be used here because it is too large for the register.&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;How can the clock be slowed down in such a case?&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;I have now made the following change and set the MAC_SUB_SECOND_INCREMENT to 21.&lt;/P&gt;&lt;P&gt;This produces a period of 952 384 638ns with an ADDEND of 0xFFFFFFFF. The formula now results in the following new ADDEND:&lt;/P&gt;&lt;P&gt;Anew = 0xFFFFFFFF * (952384638 / 1e9) = 0xF3CF7AC8&lt;/P&gt;&lt;P&gt;With this new value, I now get a period of 999 999 675ns, which is almost ideal.&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Is this the right way or am I missing something here?&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;From the description on page 3058, "70.3.8.9 System timeregister module" I don't really get the hang of how else to set it.&lt;/P&gt;&lt;P&gt;I have running an RT1170 board with the ENET-IP. INC, INC_CORR and ATCOR are used there.&amp;nbsp;But here on the N947 with the ENET_QoS I have the problems.&lt;/P&gt;&lt;P&gt;Best regards,&lt;BR /&gt;Michael&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Tue, 24 Mar 2026 09:22:01 GMT</pubDate>
    <dc:creator>michael_fischer</dc:creator>
    <dc:date>2026-03-24T09:22:01Z</dc:date>
    <item>
      <title>MCXN947: How can the period of the PPS signal be controlled with the ADDEND register?</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/MCXN947-How-can-the-period-of-the-PPS-signal-be-controlled-with/m-p/2338292#M5079</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;Reference is made to the “MCX N Reference Manual” Rev. 7.&lt;BR /&gt;The FRDM-MCX947 board with the NXP SDK v25.06.00 is used here.&lt;/P&gt;&lt;P&gt;The configuration for PTP looks like this:&lt;/P&gt;&lt;LI-CODE lang="c"&gt;#ifdef ENET_PTP1588FEATURE_REQUIRED
   enet_ptp_config_t ptpConfig;
   memset(&amp;amp;ptpConfig, 0x00, sizeof(ptpConfig));
   config.specialControl      = kENET_MulticastAllEnable | kENET_StoreAndForward;
   ptpConfig.fineUpdateEnable = true;  
   ptpConfig.ptp1588V2Enable  = true;
   ptpConfig.tsRollover       = kENET_DigitalRollover;
   config.ptpConfig           = &amp;amp;ptpConfig;
   config.ptpClkHz            = 50000000U;
#endif &lt;/LI-CODE&gt;&lt;P&gt;The digital rollover mode is used here. For the GPIO, PORT 3 pin 20 is used:&lt;/P&gt;&lt;LI-CODE lang="c"&gt;   CLOCK_EnableClock(kCLOCK_Port3);

   const port_pin_config_t pin_config = {
                                         kPORT_PullDisable,
                                         kPORT_LowPullResistor,
                                         kPORT_FastSlewRate,
                                         kPORT_PassiveFilterDisable,
                                         kPORT_OpenDrainDisable,
                                         kPORT_LowDriveStrength,
                                         kPORT_MuxAlt1,
                                         kPORT_InputBufferEnable,
                                         kPORT_InputNormal,
                                         kPORT_UnlockRegister};

   /* PORT3_20 is configured as TRIG_OUT0 */
   PORT_SetPinConfig(PORT3, 20U, &amp;amp;pin_config);

   CLOCK_EnableClock(kCLOCK_InputMux);
   INPUTMUX-&amp;gt;EXT_TRIG[0] = INPUTMUX_EXT_TRIGN_EXT_TRIG_INP(0x2F);&lt;/LI-CODE&gt;&lt;P&gt;In order to output a PPS signal at all, the TSCFUPDT bit and the ADDEND register must be set:&lt;/P&gt;&lt;LI-CODE lang="c"&gt;ENET0-&amp;gt;MAC_TIMESTAMP_CONTROL |= ENET_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK;
ENET_Ptp1588CorrectTimerInFine(ENET0, 0xFFFFFFFF);&lt;/LI-CODE&gt;&lt;P&gt;This now creates a PPS period of 1000 005 596ns. The clock runs too fast here. As PTP clock&amp;nbsp;50MHz is specified here, which leads to a MAC_SUB_SECOND_INCREMENT of 20.&lt;/P&gt;&lt;P&gt;If I have understood correctly, then the fine correction can be done via the ADDEND register.&amp;nbsp;The new ADDEND (Anew) is calculated as follows:&lt;/P&gt;&lt;P&gt;Anew = Aold * (Time wrong / 1e9)&lt;/P&gt;&lt;P&gt;In my case, this gives the following value:&lt;BR /&gt;&lt;BR /&gt;Anew = 0xFFFFFFFF * (1000005596 / 1e9) = 0x100005DE2&lt;/P&gt;&lt;P&gt;The new value cannot be used here because it is too large for the register.&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;How can the clock be slowed down in such a case?&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;I have now made the following change and set the MAC_SUB_SECOND_INCREMENT to 21.&lt;/P&gt;&lt;P&gt;This produces a period of 952 384 638ns with an ADDEND of 0xFFFFFFFF. The formula now results in the following new ADDEND:&lt;/P&gt;&lt;P&gt;Anew = 0xFFFFFFFF * (952384638 / 1e9) = 0xF3CF7AC8&lt;/P&gt;&lt;P&gt;With this new value, I now get a period of 999 999 675ns, which is almost ideal.&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Is this the right way or am I missing something here?&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;From the description on page 3058, "70.3.8.9 System timeregister module" I don't really get the hang of how else to set it.&lt;/P&gt;&lt;P&gt;I have running an RT1170 board with the ENET-IP. INC, INC_CORR and ATCOR are used there.&amp;nbsp;But here on the N947 with the ENET_QoS I have the problems.&lt;/P&gt;&lt;P&gt;Best regards,&lt;BR /&gt;Michael&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 24 Mar 2026 09:22:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/MCXN947-How-can-the-period-of-the-PPS-signal-be-controlled-with/m-p/2338292#M5079</guid>
      <dc:creator>michael_fischer</dc:creator>
      <dc:date>2026-03-24T09:22:01Z</dc:date>
    </item>
    <item>
      <title>Re: MCXN947: How can the period of the PPS signal be controlled with the ADDEND register?</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/MCXN947-How-can-the-period-of-the-PPS-signal-be-controlled-with/m-p/2338910#M5090</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/214553"&gt;@michael_fischer&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I have checked the these registers.&lt;/P&gt;
&lt;P&gt;Your method is correct.&lt;/P&gt;
&lt;P&gt;Adjust the increment (MAC_SUB_SECOND_INCREMENT) first&lt;BR /&gt;Then apply fine correction using ADDEND.&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Harry&lt;/P&gt;</description>
      <pubDate>Wed, 25 Mar 2026 02:37:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/MCXN947-How-can-the-period-of-the-PPS-signal-be-controlled-with/m-p/2338910#M5090</guid>
      <dc:creator>Harry_Zhang</dc:creator>
      <dc:date>2026-03-25T02:37:43Z</dc:date>
    </item>
    <item>
      <title>Re: MCXN947: How can the period of the PPS signal be controlled with the ADDEND register?</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/MCXN947-How-can-the-period-of-the-PPS-signal-be-controlled-with/m-p/2339308#M5099</link>
      <description>Hello &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/229957"&gt;@Harry_Zhang&lt;/a&gt;&lt;BR /&gt;&lt;BR /&gt;this means that even at a 50MHz clock an INC of 40 is allowed, and I then have to set the ADDEND register to 0x80000000.&lt;BR /&gt;I have already tested this, and I was able to set a good period here.&lt;BR /&gt;&lt;BR /&gt;In that case, however, the clock for the timestamp would run twice as fast as originally thought. Here you would have to multiply the timestamps later by 20/40 = 0.5, is that correct?&lt;BR /&gt;&lt;BR /&gt;If I set a "wrong" INC, I have to take this into account later in the timestamps, which I get from the actual hardware.&lt;BR /&gt;In the case of the slight deviation at INC = 21, I have to multiply by 20/21.&lt;BR /&gt;&lt;BR /&gt;Best regards,&lt;BR /&gt;Michael</description>
      <pubDate>Wed, 25 Mar 2026 11:39:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/MCXN947-How-can-the-period-of-the-PPS-signal-be-controlled-with/m-p/2339308#M5099</guid>
      <dc:creator>michael_fischer</dc:creator>
      <dc:date>2026-03-25T11:39:58Z</dc:date>
    </item>
    <item>
      <title>Re: MCXN947: How can the period of the PPS signal be controlled with the ADDEND register?</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/MCXN947-How-can-the-period-of-the-PPS-signal-be-controlled-with/m-p/2339686#M5104</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/214553"&gt;@michael_fischer&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I think&amp;nbsp;If the PPS signal is correctly calibrated through the ADDEND adjustment, no further software scaling of the timestamps is necessary.&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Harry&lt;/P&gt;</description>
      <pubDate>Thu, 26 Mar 2026 02:03:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/MCXN947-How-can-the-period-of-the-PPS-signal-be-controlled-with/m-p/2339686#M5104</guid>
      <dc:creator>Harry_Zhang</dc:creator>
      <dc:date>2026-03-26T02:03:56Z</dc:date>
    </item>
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