topic MCXN947 VDD_LDO_CORE Design in MCX Microcontrollers

MCXN947 VDD_LDO_CORE Design

Vasilis_Skr — Thu, 22 Jan 2026 09:09:58 GMT

First of all, hello to the NXP community.

My name is Vasilis and in my company we designed a product of ours based on the (more specifically on the MCXN947VKLT μCU, 100 pin HLQFP package).

We followed the suggestions on your power application note UG10101 and the datasheet of the μCU regarding the VDD_LDO_CORE connections:

However, when the boards arrived we found out that the μCU was not working and was sinking a lot of current, meaning it was damaged. After checking the voltage at VDD_CORE, I noticed it was substantially higher than the allowed voltage of around 1.2V (it was 2.8V).

After diving deeper into the datasheets I could only found the reference in UG10092 that states the following:

This means that the pin is internally tied to the VDD (3.3V) of the μCU and connecting it to the VDD_LDO_CORE leads to overvoltage and damage.

My questions are the following:

If we disconnect the VDD_LDO_CORE pin from the PCB manually, by lifting it up, so that it is no longer connected to VDD_CORE, will the boards be functional?
When we redesign the board, should we just leave the VDD_LDO_CORE (pin 13) floating and not connected to anything?

Thank you in advance!

P.S. could you also update the datasheet of the μCU and UG10101 with the information found in UG10092 regarding this issue? It is critical information and the lack of attention it gets leads to confusion and wrong design choices.

Re: MCXN947 VDD_LDO_CORE Design

Celeste_Liu — Fri, 23 Jan 2026 04:11:46 GMT

Hello @Vasilis_Skr ,

Thanks for your post. Hope you are doing great!

I have reviewed your question. Regarding the HLQFP 100-pin package, Pin 13 (VDD_LDO_CORE, VDD_P2, and VDD are bonded to Pin 13) must be connected to the VDD voltage.

I recommend that you directly refer to UG10343. Although it is written for the MCXN23x, the same applies to MCXN94/54x.

https://www.nxp.com/webapp/Download?colCode=UG10343&location=null&isHTMLorPDF=HTML

For DCDC mode, please refer to "section 3.1 DCDC mode "

In addition, I have noted your suggestion and I think it is reasonable. Thank you for your feedback. I will forward your suggestion to our internal team. We will continue to improve the quality of our documentation.

Celeste

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Re: MCXN947 VDD_LDO_CORE Design

Celeste_Liu — Mon, 26 Jan 2026 02:27:42 GMT

Hello @Vasilis_Skr ,

Please see the feedback from our internal:

UG10092 (https://www.nxp.com/webapp/Download?colCode=UG10092&isHTMLorPDF=HTML) should be the User guide to use. Furthermore, there is a design checklist posted on the MCXN947 webpage that should also be used when designing in these devices (https://www.nxp.com/webapp/Download?colCode=MCXNSERIES-DESIGN-IN-CHECKLIST&appType=license).

There is a new version of UG10092 that will be published soon (rev 5). Customers should not have problems with this version.

Hope it helps.

Celeste

Re: MCXN947 VDD_LDO_CORE Design

Vasilis_Skr — Mon, 26 Jan 2026 08:59:53 GMT

Hey @Celeste_Liu,

First of all, thank you for your replies and suggestions.

Regarding UG10343, this datasheet is more detailed than UG10092 on the usage of the DCDC converter of the μCU and it shows clearly that VDD is tied internally to VDD_P2 and VDD_LDO_CORE.

I verified that this is the case also in our system, since I lifted pin 13 of MCXN947VKLT (100HQLFP package) from the PCB, therefore disconnecting VDD_LDO_CORE from VDD_CORE and I can measure 3V3 on it directly. After doing this the μCU works fine, so I will correct the design mistake in the next iteration.

Also, the checklist in excel form is extremely useful.

Maybe another suggestion from my side, to avoid that someone repeats the mistake we did, would be to include the difference in the schematics between the BGA and HLQFP packages regarding power connections.

Thank you very much for the help and prompt replies!

Best Regards,

Vasilis Skr.

Re: MCXN947 VDD_LDO_CORE Design

Vasilis_Skr — Mon, 26 Jan 2026 09:11:43 GMT

Hey @Celeste_Liu,

The thing I forgot to ask for the next design iteration in my previous post is whether pin 13 has to always be connected to VDD?

Is a decoupling capacitor also needed?

Or can it be left floating?

Thank you in advance!

Best Regards,

Vasilis Skr.

Re: MCXN947 VDD_LDO_CORE Design

Celeste_Liu — Tue, 27 Jan 2026 04:31:41 GMT

Hello @Vasilis_Skr ,

I am very glad to help you.

would be to include the difference in the schematics between the BGA and HLQFP packages regarding power connections.

->> Could you please provide more details? Which document do you think these contents should be added to? I will share your suggestions with the internal team, but I cannot guarantee that they will be adopted. Sorry for any inconvenience.

The thing I forgot to ask for the next design iteration in my previous post is whether pin 13 has to always be connected to VDD?

Is a decoupling capacitor also needed?

->> Yes, pin 13 should always be connected to VDD. Please also add decoupling capacitors: one 1 µF capacitor and three 0.1 µF capacitors, as shown in the diagram below.

Let me explain: The note " VDD_LDO_CORE is internally bonded to VDD in the HLQFP package." in UG10092 means that VDD_LDO_CORE is boned to VDD pin, therefore, it must be connected to the VDD supply.

Have a nice day.

Celeste

Re: MCXN947 VDD_LDO_CORE Design

Vasilis_Skr — Tue, 27 Jan 2026 08:23:57 GMT

Hey @Celeste_Liu

I think mentioning more adding the following pictures from UG10343 to UG10092 will help other designers have a clearer picture on what to do with the pins :).

Thanks a lot for your help!

Best Regards,

Vasilis

Re: MCXN947 VDD_LDO_CORE Design

Celeste_Liu — Tue, 27 Jan 2026 08:50:32 GMT

Hello @Vasilis_Skr

Understood. Thanks for your suggestion, I will pass it on to the internal team.

Wish all the best!

Celeste