<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: Interfacing IMRT1170-EVKB DevKit with a 12 bit pixel monochrome camera with 2 lane MIPI in MCX Microcontrollers</title>
    <link>https://community.nxp.com/t5/MCX-Microcontrollers/Interfacing-IMRT1170-EVKB-DevKit-with-a-12-bit-pixel-monochrome/m-p/2200771#M4326</link>
    <description>&lt;P&gt;Hi, have done most of the workaround but still not able to receive the data send from FPGA.&lt;BR /&gt;&lt;BR /&gt;Q1 ) I wanted to ask about the connected i am using in mipi .&lt;BR /&gt;&lt;BR /&gt;Image 1 :&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="jyothz_0-1762507846761.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/364429i944B61AF2798374C/image-size/medium?v=v2&amp;amp;px=400" role="button" title="jyothz_0-1762507846761.png" alt="jyothz_0-1762507846761.png" /&gt;&lt;/span&gt;&lt;BR /&gt;image 2:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="jyothz_1-1762507938775.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/364432iBF21E0BAEC66EB17/image-size/medium?v=v2&amp;amp;px=400" role="button" title="jyothz_1-1762507938775.png" alt="jyothz_1-1762507938775.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;as shown in above "image 1" of the connected from the NXP Schematics there are many functional pins , like PWR_EN and others but in the connecter i have designed only has 3 set of differential pairs 2 data lanes and 1 clock lane with ground are these much connections are only needed to establish a valid connection in mipi with the FPGA Replacing OVA5640 camera or any other pins are been validated for proper connection.&lt;BR /&gt;&lt;BR /&gt;Q2) I have also observed while Initializing MIPI CSI2 RX in NXP IMXRT1170 controller the while initializing the MIPI&amp;nbsp; CSI@ RX registers some hard_fault or bus error occurs due to which the code gets hang there and after that i am not able to flash code causing "&lt;SPAN&gt;error closing down debug session - Nn(05). Wire ACK Fault in DAP access" error&lt;BR /&gt;&lt;BR /&gt;Please help with these doubts so that i can move forward with my work since i am stuck for a long.&lt;BR /&gt;&lt;BR /&gt;Thankyou for your time and effort.&lt;BR /&gt;&lt;BR /&gt;Jyothish&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Fri, 07 Nov 2025 09:41:01 GMT</pubDate>
    <dc:creator>jyothz</dc:creator>
    <dc:date>2025-11-07T09:41:01Z</dc:date>
    <item>
      <title>Interfacing IMRT1170-EVKB DevKit with a 12 bit pixel monochrome camera with 2 lane MIPI</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Interfacing-IMRT1170-EVKB-DevKit-with-a-12-bit-pixel-monochrome/m-p/2182707#M4157</link>
      <description>&lt;P&gt;Hi Team,&lt;/P&gt;&lt;P&gt;We are currently working on interfacing the &lt;STRONG&gt;i.MX RT1170-EVKB&lt;/STRONG&gt; board with a camera using a &lt;STRONG&gt;2-lane MIPI interface&lt;/STRONG&gt;. In our setup, all camera control signals are managed by an &lt;STRONG&gt;FPGA&lt;/STRONG&gt;, while the i.MX RT1170 board is responsible only for &lt;STRONG&gt;receiving image data&lt;/STRONG&gt; from the FPGA and &lt;STRONG&gt;streaming it to the host system&lt;/STRONG&gt;.&lt;/P&gt;&lt;P&gt;We have attempted to modify the &lt;STRONG&gt;“uvc_rgb_imxrt1170”&lt;/STRONG&gt; example project by bypassing the camera initialization and I²C control sequences, since the camera is managed externally. However, we have not yet been able to verify whether the board is successfully receiving data over the MIPI interface.&lt;/P&gt;&lt;P&gt;The camera specifications are as follows:&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;&lt;P&gt;Pixel format: 12-bit monochrome&lt;/P&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P&gt;Resolution: 2048 × 2048&lt;/P&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P&gt;Data source: FPGA (via 2-lane MIPI)&lt;/P&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;Before proceeding further, we would like clarification on the following points:&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;&lt;P&gt;Is it feasible to interface the i.MX RT1170-EVKB with an &lt;STRONG&gt;FPGA-based MIPI source&lt;/STRONG&gt; by replacing the OV5640 camera?&lt;/P&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P&gt;Can the existing &lt;STRONG&gt;PXP (Pixel Pipeline)&lt;/STRONG&gt; module handle the 12-bit monochrome data format described above?&lt;/P&gt;&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;For reference, we have attached details of the &lt;STRONG&gt;MIPI connector&lt;/STRONG&gt; used and the &lt;STRONG&gt;example project&lt;/STRONG&gt; originally designed for streaming data from the OV5640 camera.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="jyothz_0-1759986908362.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/359998iAC95BF5F351515A1/image-size/medium?v=v2&amp;amp;px=400" role="button" title="jyothz_0-1759986908362.png" alt="jyothz_0-1759986908362.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;FPGA to IMXRT1170 connector (J2 in IMX BOARD)&lt;/P&gt;&lt;P&gt;Please Go through and Respond&amp;nbsp;&lt;BR /&gt;Any information regarding this will be much valuable and helpful.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Thank you for your guidance and support.&lt;BR /&gt;Jyothish&lt;/P&gt;</description>
      <pubDate>Thu, 09 Oct 2025 05:26:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Interfacing-IMRT1170-EVKB-DevKit-with-a-12-bit-pixel-monochrome/m-p/2182707#M4157</guid>
      <dc:creator>jyothz</dc:creator>
      <dc:date>2025-10-09T05:26:04Z</dc:date>
    </item>
    <item>
      <title>Re: Interfacing IMRT1170-EVKB DevKit with a 12 bit pixel monochrome camera with 2 lane MIPI</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Interfacing-IMRT1170-EVKB-DevKit-with-a-12-bit-pixel-monochrome/m-p/2183737#M4179</link>
      <description>&lt;P&gt;&lt;SPAN&gt;Hi,&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;It is feasible to interface the i.MX RT1170-EVKB with an FPGA-based MIPI source, but the PXP module will require data format conversion to handle 12-bit monochrome data.&lt;/SPAN&gt;&lt;/P&gt;
&lt;UL&gt;
&lt;LI&gt;&lt;SPAN&gt;Q1.&amp;nbsp;&lt;/SPAN&gt;FPGA-based MIPI Source Interface:&amp;nbsp;Interfacing an FPGA that acts as a MIPI CSI-2 camera source is possible. The i.MX RT1170-EVKB is equipped with a MIPI Camera Module Connector (J2) designed for this purpose. But we don't have such solution to support by using FPGA-based MIPI source.&lt;/LI&gt;
&lt;LI&gt;Q2. PXP and 12-bit Monochrome Data: The PXP (Pixel Pipeline) is a 2D graphics accelerator capable of operations like color space conversion, rotation, and resizing&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;,&lt;/SPAN&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;. However, it &lt;U&gt;does not&lt;/U&gt; have native support for a 12-bit monochrome (grayscale) input format.&lt;/SPAN&gt;
&lt;UL&gt;
&lt;LI class=""&gt;&lt;STRONG class=""&gt;Supported PXP Formats&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;: The PXP supports a variety of RGB and YUV formats, including 8-bit monochrome (&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;CODE class=""&gt;Y8&lt;/CODE&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;) and 4-bit monochrome (&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;CODE class=""&gt;Y4&lt;/CODE&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;),. There is no documented support for a 12-bit monochrome (&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;CODE class=""&gt;Y12&lt;/CODE&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;) input.&lt;/LI&gt;
&lt;LI&gt;&lt;SPAN&gt;&lt;STRONG class=""&gt;Required Workaround&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;: To process the image with the PXP, the 12-bit monochrome data must be converted into a supported format&lt;/SPAN&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;EM class=""&gt;before&lt;/EM&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;it is passed to the PXP.&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/LI&gt;
&lt;/UL&gt;
&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 10 Oct 2025 08:44:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Interfacing-IMRT1170-EVKB-DevKit-with-a-12-bit-pixel-monochrome/m-p/2183737#M4179</guid>
      <dc:creator>Sam_Gao</dc:creator>
      <dc:date>2025-10-10T08:44:32Z</dc:date>
    </item>
    <item>
      <title>Re: Interfacing IMRT1170-EVKB DevKit with a 12 bit pixel monochrome camera with 2 lane MIPI</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Interfacing-IMRT1170-EVKB-DevKit-with-a-12-bit-pixel-monochrome/m-p/2186255#M4212</link>
      <description>&lt;P&gt;Apologies for the delayed response, and thank you for your valuable input earlier — it helped us confirm that the setup is indeed feasible.&lt;BR /&gt;&lt;BR /&gt;We have an additional query: In our setup, an FPGA is connected to a camera module and continuously streams image data to the i.MX RT1170 controller via the MIPI interface. Since the FPGA handles all communication with the camera, we have excluded the I2C-based camera initialization from the i.MX RT1170 side.&lt;BR /&gt;Our question is: Will the MIPI interface on the i.MX RT1170 still function correctly if we completely remove the I2C camera initialization sequence, considering that the FPGA does not require any I2C interaction? Or, are there any I2C-dependent flags, registers, or status bits within the i.MX RT1170 MIPI subsystem that are mandatory for proper MIPI operation?&lt;BR /&gt;&lt;BR /&gt;Thank you for your time and guidance.&lt;BR /&gt;&lt;BR /&gt;Best regards,&lt;BR /&gt;Jyothish&lt;/P&gt;</description>
      <pubDate>Wed, 15 Oct 2025 05:09:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Interfacing-IMRT1170-EVKB-DevKit-with-a-12-bit-pixel-monochrome/m-p/2186255#M4212</guid>
      <dc:creator>jyothz</dc:creator>
      <dc:date>2025-10-15T05:09:59Z</dc:date>
    </item>
    <item>
      <title>Re: Interfacing IMRT1170-EVKB DevKit with a 12 bit pixel monochrome camera with 2 lane MIPI</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Interfacing-IMRT1170-EVKB-DevKit-with-a-12-bit-pixel-monochrome/m-p/2189083#M4241</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;I2C and MIPI are independent. MIPI and I2C(I2C_6) are used to control the camera in the RT1170-EVKB board, but there is no dependency between them.&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 20 Oct 2025 09:12:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Interfacing-IMRT1170-EVKB-DevKit-with-a-12-bit-pixel-monochrome/m-p/2189083#M4241</guid>
      <dc:creator>Sam_Gao</dc:creator>
      <dc:date>2025-10-20T09:12:04Z</dc:date>
    </item>
    <item>
      <title>Re: Interfacing IMRT1170-EVKB DevKit with a 12 bit pixel monochrome camera with 2 lane MIPI</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Interfacing-IMRT1170-EVKB-DevKit-with-a-12-bit-pixel-monochrome/m-p/2200771#M4326</link>
      <description>&lt;P&gt;Hi, have done most of the workaround but still not able to receive the data send from FPGA.&lt;BR /&gt;&lt;BR /&gt;Q1 ) I wanted to ask about the connected i am using in mipi .&lt;BR /&gt;&lt;BR /&gt;Image 1 :&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="jyothz_0-1762507846761.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/364429i944B61AF2798374C/image-size/medium?v=v2&amp;amp;px=400" role="button" title="jyothz_0-1762507846761.png" alt="jyothz_0-1762507846761.png" /&gt;&lt;/span&gt;&lt;BR /&gt;image 2:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="jyothz_1-1762507938775.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/364432iBF21E0BAEC66EB17/image-size/medium?v=v2&amp;amp;px=400" role="button" title="jyothz_1-1762507938775.png" alt="jyothz_1-1762507938775.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;as shown in above "image 1" of the connected from the NXP Schematics there are many functional pins , like PWR_EN and others but in the connecter i have designed only has 3 set of differential pairs 2 data lanes and 1 clock lane with ground are these much connections are only needed to establish a valid connection in mipi with the FPGA Replacing OVA5640 camera or any other pins are been validated for proper connection.&lt;BR /&gt;&lt;BR /&gt;Q2) I have also observed while Initializing MIPI CSI2 RX in NXP IMXRT1170 controller the while initializing the MIPI&amp;nbsp; CSI@ RX registers some hard_fault or bus error occurs due to which the code gets hang there and after that i am not able to flash code causing "&lt;SPAN&gt;error closing down debug session - Nn(05). Wire ACK Fault in DAP access" error&lt;BR /&gt;&lt;BR /&gt;Please help with these doubts so that i can move forward with my work since i am stuck for a long.&lt;BR /&gt;&lt;BR /&gt;Thankyou for your time and effort.&lt;BR /&gt;&lt;BR /&gt;Jyothish&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 07 Nov 2025 09:41:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Interfacing-IMRT1170-EVKB-DevKit-with-a-12-bit-pixel-monochrome/m-p/2200771#M4326</guid>
      <dc:creator>jyothz</dc:creator>
      <dc:date>2025-11-07T09:41:01Z</dc:date>
    </item>
    <item>
      <title>Re: Interfacing IMRT1170-EVKB DevKit with a 12 bit pixel monochrome camera with 2 lane MIPI</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Interfacing-IMRT1170-EVKB-DevKit-with-a-12-bit-pixel-monochrome/m-p/2204390#M4359</link>
      <description>&lt;P&gt;&lt;SPAN&gt;please refer to application notes AN13573 for MIPI CSI and AN12940 for MIPI DSI configurations on the RT1170 platform.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;&lt;A href="https://docs.nxp.com/bundle/AN13573/page/topics/features_differences_between_imx_8m_and_imx_rt_par.html" target="_blank" rel="noopener" shape="rect"&gt;https://docs.nxp.com/bundle/AN13573/page/topics/features_differences_between_imx_8m_and_imx_rt_par.html&lt;/A&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;&lt;A href="https://www.nxp.com/docs/en/application-note/AN12940.pdf" target="_blank" rel="noopener" shape="rect"&gt;https://www.nxp.com/docs/en/application-note/AN12940.pdf&lt;/A&gt;&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 13 Nov 2025 09:56:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Interfacing-IMRT1170-EVKB-DevKit-with-a-12-bit-pixel-monochrome/m-p/2204390#M4359</guid>
      <dc:creator>Sam_Gao</dc:creator>
      <dc:date>2025-11-13T09:56:42Z</dc:date>
    </item>
  </channel>
</rss>

