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    <title>topic Query Regarding NPU Configuration on i.MX8M Plus in MCX Microcontrollers</title>
    <link>https://community.nxp.com/t5/MCX-Microcontrollers/Query-Regarding-NPU-Configuration-on-i-MX8M-Plus/m-p/2194772#M4276</link>
    <description>&lt;P&gt;Hi Sir,&lt;/P&gt;&lt;P&gt;I am Samudralankaiah from Vconnectech Systems Pvt. Ltd. Recently, we purchased the i.MX8M Plus evaluation board for our Smart IP Camera project. We are currently evaluating the camera performance and would like to understand the following details regarding the NPU:&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;&lt;P&gt;The number of NPU cores available on the i.MX8M Plus.&lt;/P&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P&gt;Configuration attributes such as memory caching, job assignment to individual NPU cores, and the frameworks/libraries/APIs used to configure or access the NPU (apart from the VX delegate used for executing inference on the NPU).&lt;/P&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P&gt;Additionally, in the future, if we want to execute an inference on a specific NPU core, how can that be configured?&lt;/P&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;Kindly provide the relevant details or documentation regarding the above.&lt;/P&gt;&lt;P&gt;Best regards,&lt;BR /&gt;&lt;STRONG&gt;Samudralankaiah&lt;/STRONG&gt;&lt;BR /&gt;Vconnectech Systems Pvt. Ltd&lt;/P&gt;</description>
    <pubDate>Wed, 29 Oct 2025 04:53:14 GMT</pubDate>
    <dc:creator>Samudralankaiah</dc:creator>
    <dc:date>2025-10-29T04:53:14Z</dc:date>
    <item>
      <title>Query Regarding NPU Configuration on i.MX8M Plus</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Query-Regarding-NPU-Configuration-on-i-MX8M-Plus/m-p/2194772#M4276</link>
      <description>&lt;P&gt;Hi Sir,&lt;/P&gt;&lt;P&gt;I am Samudralankaiah from Vconnectech Systems Pvt. Ltd. Recently, we purchased the i.MX8M Plus evaluation board for our Smart IP Camera project. We are currently evaluating the camera performance and would like to understand the following details regarding the NPU:&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;&lt;P&gt;The number of NPU cores available on the i.MX8M Plus.&lt;/P&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P&gt;Configuration attributes such as memory caching, job assignment to individual NPU cores, and the frameworks/libraries/APIs used to configure or access the NPU (apart from the VX delegate used for executing inference on the NPU).&lt;/P&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P&gt;Additionally, in the future, if we want to execute an inference on a specific NPU core, how can that be configured?&lt;/P&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;Kindly provide the relevant details or documentation regarding the above.&lt;/P&gt;&lt;P&gt;Best regards,&lt;BR /&gt;&lt;STRONG&gt;Samudralankaiah&lt;/STRONG&gt;&lt;BR /&gt;Vconnectech Systems Pvt. Ltd&lt;/P&gt;</description>
      <pubDate>Wed, 29 Oct 2025 04:53:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Query-Regarding-NPU-Configuration-on-i-MX8M-Plus/m-p/2194772#M4276</guid>
      <dc:creator>Samudralankaiah</dc:creator>
      <dc:date>2025-10-29T04:53:14Z</dc:date>
    </item>
    <item>
      <title>Re: Query Regarding NPU Configuration on i.MX8M Plus</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Query-Regarding-NPU-Configuration-on-i-MX8M-Plus/m-p/2194922#M4278</link>
      <description>&lt;P&gt;Hi,&lt;BR /&gt;&lt;BR /&gt;Continue in SFDC.&lt;BR /&gt;&lt;BR /&gt;Best Regards,&lt;BR /&gt;Zhiming&lt;/P&gt;</description>
      <pubDate>Wed, 29 Oct 2025 07:59:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Query-Regarding-NPU-Configuration-on-i-MX8M-Plus/m-p/2194922#M4278</guid>
      <dc:creator>Zhiming_Liu</dc:creator>
      <dc:date>2025-10-29T07:59:32Z</dc:date>
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