<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Zephyr: Ramloader: RAM load not working on mimxrt1064-evk and zephyr4.1. in MCX Microcontrollers</title>
    <link>https://community.nxp.com/t5/MCX-Microcontrollers/Zephyr-Ramloader-RAM-load-not-working-on-mimxrt1064-evk-and/m-p/2122619#M3391</link>
    <description>&lt;DIV&gt;&lt;SPAN&gt;I followed the &lt;/SPAN&gt;&lt;SPAN&gt;`&lt;A href="https://docs.nxp.com/bundle/AN14597/page/topics/relocating_all_code_andor_all_data_to_sdram.html" target="_blank" rel="noopener"&gt;Relocating to SDRAM&lt;/A&gt;`&lt;/SPAN&gt;&lt;SPAN&gt; example with &lt;LI-PRODUCT title="MIMXRT1064-EVK" id="MIMXRT1064-EVK"&gt;&lt;/LI-PRODUCT&gt;&amp;nbsp;. I would like to ask about it. Because ram load did not work as expected.&lt;/SPAN&gt;&lt;/DIV&gt;&lt;P&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;DIV&gt;1. I used &lt;U&gt;MCUXpresso for vs code extension&lt;/U&gt; to get &lt;STRONG&gt;blinky sample&lt;/STRONG&gt; from nxp_zephyr_nxp_v4_1_0 repository.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;2.&lt;/SPAN&gt;&lt;SPAN&gt; Added boards/mimxrt1064_evk.conf.&lt;/SPAN&gt;&lt;/DIV&gt;&lt;LI-CODE lang="ruby"&gt;CONFIG_NXP_FLEXSPI_ROM_RAMLOADER=y​&lt;/LI-CODE&gt;&lt;P&gt;&lt;BR /&gt;&lt;SPAN&gt;3.&lt;/SPAN&gt;&lt;SPAN&gt; Added boards/mimxrt1064_evk.overlay.&lt;/SPAN&gt;&lt;/P&gt;&lt;LI-CODE lang="ruby"&gt;/ {
	chosen {
		zephyr,flash = &amp;amp;sdram_code;
		zephyr,sram = &amp;amp;sdram_data;
    };
};

&amp;amp;sdram0 {
        #address-cells = &amp;lt; 0x1 &amp;gt;;
        #size-cells = &amp;lt; 0x1 &amp;gt;;
        /* Divide SDRAM into two partitions for Code and Data */
        sdram_code: memory@0 {
                device_type = "memory";
                reg = &amp;lt;0x00000000 DT_SIZE_M(16)&amp;gt;;

        };
        sdram_data: memory@1000000 {
                device_type = "memory";
                reg = &amp;lt;0x01000000 DT_SIZE_M(16)&amp;gt;;
        };
};&lt;/LI-CODE&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;4. build project. FLASH and RAM regions below:&lt;/SPAN&gt;&lt;/DIV&gt;&lt;LI-CODE lang="ruby"&gt;Memory region         Used Size  Region Size  %age Used
           SDRAM:          0 GB        32 MB      0.00%
           FLASH:       32822 B        32 MB      0.10%
             RAM:        4288 B        16 MB      0.03%&lt;/LI-CODE&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;5. build/zephyr/zephyr.map below:&lt;/SPAN&gt;&lt;/DIV&gt;&lt;LI-CODE lang="markup"&gt;&amp;lt;Text start region&amp;gt;
text            0x00000000000022c0     0x3648
                0x00000000000022c0                __text_region_start = .

&amp;lt;Text end region&amp;gt;
                0x0000000000005908                . = ALIGN (0x4)
                0x0000000000005908                __text_region_end = .

&amp;lt;Data start region&amp;gt;
datas           0x0000000001000000       0x1c load address 0x0000000080008000
                0x0000000001000000                __data_region_start = .
                0x0000000001000000                __data_start = .

&amp;lt;Data end region&amp;gt;
                0x0000000001000032                _net_buf_pool_list_end = .
                0x0000000001000032                __data_region_end = .&lt;/LI-CODE&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Why is the relocation for Ramload not working properly? Please let me know if I missed anything in following the guide.&lt;/DIV&gt;</description>
    <pubDate>Wed, 25 Jun 2025 01:29:59 GMT</pubDate>
    <dc:creator>mastergbc</dc:creator>
    <dc:date>2025-06-25T01:29:59Z</dc:date>
    <item>
      <title>Zephyr: Ramloader: RAM load not working on mimxrt1064-evk and zephyr4.1.</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Zephyr-Ramloader-RAM-load-not-working-on-mimxrt1064-evk-and/m-p/2122619#M3391</link>
      <description>&lt;DIV&gt;&lt;SPAN&gt;I followed the &lt;/SPAN&gt;&lt;SPAN&gt;`&lt;A href="https://docs.nxp.com/bundle/AN14597/page/topics/relocating_all_code_andor_all_data_to_sdram.html" target="_blank" rel="noopener"&gt;Relocating to SDRAM&lt;/A&gt;`&lt;/SPAN&gt;&lt;SPAN&gt; example with &lt;LI-PRODUCT title="MIMXRT1064-EVK" id="MIMXRT1064-EVK"&gt;&lt;/LI-PRODUCT&gt;&amp;nbsp;. I would like to ask about it. Because ram load did not work as expected.&lt;/SPAN&gt;&lt;/DIV&gt;&lt;P&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;DIV&gt;1. I used &lt;U&gt;MCUXpresso for vs code extension&lt;/U&gt; to get &lt;STRONG&gt;blinky sample&lt;/STRONG&gt; from nxp_zephyr_nxp_v4_1_0 repository.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;2.&lt;/SPAN&gt;&lt;SPAN&gt; Added boards/mimxrt1064_evk.conf.&lt;/SPAN&gt;&lt;/DIV&gt;&lt;LI-CODE lang="ruby"&gt;CONFIG_NXP_FLEXSPI_ROM_RAMLOADER=y​&lt;/LI-CODE&gt;&lt;P&gt;&lt;BR /&gt;&lt;SPAN&gt;3.&lt;/SPAN&gt;&lt;SPAN&gt; Added boards/mimxrt1064_evk.overlay.&lt;/SPAN&gt;&lt;/P&gt;&lt;LI-CODE lang="ruby"&gt;/ {
	chosen {
		zephyr,flash = &amp;amp;sdram_code;
		zephyr,sram = &amp;amp;sdram_data;
    };
};

&amp;amp;sdram0 {
        #address-cells = &amp;lt; 0x1 &amp;gt;;
        #size-cells = &amp;lt; 0x1 &amp;gt;;
        /* Divide SDRAM into two partitions for Code and Data */
        sdram_code: memory@0 {
                device_type = "memory";
                reg = &amp;lt;0x00000000 DT_SIZE_M(16)&amp;gt;;

        };
        sdram_data: memory@1000000 {
                device_type = "memory";
                reg = &amp;lt;0x01000000 DT_SIZE_M(16)&amp;gt;;
        };
};&lt;/LI-CODE&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;4. build project. FLASH and RAM regions below:&lt;/SPAN&gt;&lt;/DIV&gt;&lt;LI-CODE lang="ruby"&gt;Memory region         Used Size  Region Size  %age Used
           SDRAM:          0 GB        32 MB      0.00%
           FLASH:       32822 B        32 MB      0.10%
             RAM:        4288 B        16 MB      0.03%&lt;/LI-CODE&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;5. build/zephyr/zephyr.map below:&lt;/SPAN&gt;&lt;/DIV&gt;&lt;LI-CODE lang="markup"&gt;&amp;lt;Text start region&amp;gt;
text            0x00000000000022c0     0x3648
                0x00000000000022c0                __text_region_start = .

&amp;lt;Text end region&amp;gt;
                0x0000000000005908                . = ALIGN (0x4)
                0x0000000000005908                __text_region_end = .

&amp;lt;Data start region&amp;gt;
datas           0x0000000001000000       0x1c load address 0x0000000080008000
                0x0000000001000000                __data_region_start = .
                0x0000000001000000                __data_start = .

&amp;lt;Data end region&amp;gt;
                0x0000000001000032                _net_buf_pool_list_end = .
                0x0000000001000032                __data_region_end = .&lt;/LI-CODE&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Why is the relocation for Ramload not working properly? Please let me know if I missed anything in following the guide.&lt;/DIV&gt;</description>
      <pubDate>Wed, 25 Jun 2025 01:29:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Zephyr-Ramloader-RAM-load-not-working-on-mimxrt1064-evk-and/m-p/2122619#M3391</guid>
      <dc:creator>mastergbc</dc:creator>
      <dc:date>2025-06-25T01:29:59Z</dc:date>
    </item>
    <item>
      <title>Re: Zephyr: Ramloader: RAM load not working on mimxrt1064-evk and zephyr4.1.</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Zephyr-Ramloader-RAM-load-not-working-on-mimxrt1064-evk-and/m-p/2123852#M3405</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/252012"&gt;@mastergbc&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;Thanks for your interest in NXP MIMXRT series!&lt;/P&gt;
&lt;P&gt;I followed the Chapter 3.3.2 and had the same issue. I am asking for expert help to confirm this issue, please wait for my news. Thanks!&lt;/P&gt;
&lt;P&gt;Best regards,&lt;BR /&gt;Gavin&lt;/P&gt;</description>
      <pubDate>Thu, 26 Jun 2025 09:12:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Zephyr-Ramloader-RAM-load-not-working-on-mimxrt1064-evk-and/m-p/2123852#M3405</guid>
      <dc:creator>Gavin_Jia</dc:creator>
      <dc:date>2025-06-26T09:12:57Z</dc:date>
    </item>
    <item>
      <title>Re: Zephyr: Ramloader: RAM load not working on mimxrt1064-evk and zephyr4.1.</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Zephyr-Ramloader-RAM-load-not-working-on-mimxrt1064-evk-and/m-p/2124884#M3422</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/252012"&gt;@mastergbc&lt;/a&gt;&amp;nbsp;Can you try adding address translation for the child nodes?&lt;BR /&gt;&lt;BR /&gt;I believe that the address translation was either performed automatically or the child nodes were indexing into the parent node in a previous version of zephyr.&lt;/P&gt;
&lt;LI-CODE lang="c"&gt;&amp;amp;sdram0 {
	ranges = &amp;lt;0x00000000 0x80000000 DT_SIZE_M(32) &amp;gt;;
	#address-cells = &amp;lt; 0x1 &amp;gt;;
	#size-cells = &amp;lt; 0x1 &amp;gt;;
	/*Divide SDRAM into two partitions for Code and Data */
	sdram_code: memory@0 {
		device_type = "memory";
		reg = &amp;lt;0x00000000 DT_SIZE_M(16)&amp;gt;;
	};
	sdram_data: memory@1000000 {
		device_type = "memory";
		reg = &amp;lt;0x01000000 DT_SIZE_M(16)&amp;gt;;
	};
};&lt;/LI-CODE&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;The ranges property will translate the base address in SDRAM to the CPU address.&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 27 Jun 2025 16:26:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Zephyr-Ramloader-RAM-load-not-working-on-mimxrt1064-evk-and/m-p/2124884#M3422</guid>
      <dc:creator>jacobwienecke</dc:creator>
      <dc:date>2025-06-27T16:26:58Z</dc:date>
    </item>
    <item>
      <title>Re: Zephyr: Ramloader: RAM load not working on mimxrt1064-evk and zephyr4.1.</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Zephyr-Ramloader-RAM-load-not-working-on-mimxrt1064-evk-and/m-p/2125409#M3438</link>
      <description>Good solution.</description>
      <pubDate>Mon, 30 Jun 2025 07:16:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Zephyr-Ramloader-RAM-load-not-working-on-mimxrt1064-evk-and/m-p/2125409#M3438</guid>
      <dc:creator>mastergbc</dc:creator>
      <dc:date>2025-06-30T07:16:31Z</dc:date>
    </item>
  </channel>
</rss>

