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    <title>topic Re: Writing QSPI Flash on MCXN947 board. in MCX Microcontrollers</title>
    <link>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2077049#M2860</link>
    <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/247126"&gt;@takagi_y&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;You can&amp;nbsp;write from the SEC tool, this proves that the FCB produced by SEC is correct.&lt;/P&gt;
&lt;P&gt;So i think you can flash the correct FCB to 0x80000400.&lt;/P&gt;
&lt;P&gt;And then delete&amp;nbsp;mcxn_flexspi_nor_config.c and&amp;nbsp;mcxn_flexspi_nor_config.h in MCUXpresso.&lt;/P&gt;
&lt;P&gt;Because they generate the NEW FCB and flash in&amp;nbsp;0x80000400.&lt;/P&gt;
&lt;P&gt;And you can debug it.&lt;/P&gt;
&lt;P&gt;I tested, i generate the FCB.bin through the SEC tool. and flash it into 0x80000400.&lt;/P&gt;
&lt;P&gt;And i can debug it successfully.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Harry_Zhang_0-1744193877363.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/332272iC5E03CEE11937E36/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Harry_Zhang_0-1744193877363.png" alt="Harry_Zhang_0-1744193877363.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;To summarize, put the correct FCB into 0x80000400, and put the correct application into 0x80001000.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Harry&lt;/P&gt;</description>
    <pubDate>Wed, 09 Apr 2025 10:26:31 GMT</pubDate>
    <dc:creator>Harry_Zhang</dc:creator>
    <dc:date>2025-04-09T10:26:31Z</dc:date>
    <item>
      <title>Writing QSPI Flash on MCXN947 board.</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2055980#M2589</link>
      <description>&lt;P&gt;The other day I asked a question about writing flash to FRDM-MCXN947.&lt;/P&gt;&lt;P&gt;Thanks to your answer, I am now able to write to FRDM-MCXN947.&lt;/P&gt;&lt;P&gt;Thank you.&lt;/P&gt;&lt;P&gt;This time I would like to ask a question about writing flash to another board using MCXN947.&lt;/P&gt;&lt;P&gt;I tried to write to this board using the writing method for FRDM-MCXN947 as a reference, but an error occurred.&lt;/P&gt;&lt;P&gt;Below is the content of the console at that time.&lt;/P&gt;&lt;TABLE border="1" width="100%"&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD width="100%"&gt;NXP: MCXN947&lt;BR /&gt;DAP stride is 1024 bytes (256 words)&lt;BR /&gt;Inspected v.2 External Flash Device on SPI using SFDP JEDEC ID MCXN9xx_SFDP_FlexSPI.cfx&lt;BR /&gt;Image 'MCXN9xx_SFDP_FlexSPI Sep 19 2024 18:18:31'&lt;BR /&gt;Opening flash driver MCXN9xx_SFDP_FlexSPI.cfx&lt;BR /&gt;VECTRESET requested, but not supported on ARMv8-M CPUs. Using SOFTRESET instead.&lt;BR /&gt;Using SOFT reset to run the flash driver&lt;BR /&gt;Driver V.2 dynamic startup failed - driver Init provided no flash parameters&lt;BR /&gt;driver describes no sectors starting at 0x80000000&lt;BR /&gt;Flash Driver V.2 startup failed - rc Ef(58): Flash Driver describes no sectors at its base address&lt;BR /&gt;chip initialization failed - Ef(58): Flash Driver describes no sectors at its base address&lt;BR /&gt;failed to initialize flash driver MCXN9xx_SFDP_FlexSPI.cfx&lt;BR /&gt;Inspected v.2 External Flash Device on SPI using SFDP JEDEC ID MCXN9xx_SFDP_FlexSPI.cfx&lt;BR /&gt;Image 'MCXN9xx_SFDP_FlexSPI Sep 19 2024 18:18:31'&lt;BR /&gt;Opening flash driver MCXN9xx_SFDP_FlexSPI.cfx&lt;BR /&gt;VECTRESET requested, but not supported on ARMv8-M CPUs. Using SOFTRESET instead.&lt;BR /&gt;Using SOFT reset to run the flash driver&lt;BR /&gt;Driver V.2 dynamic startup failed - driver Init provided no flash parameters&lt;BR /&gt;driver describes no sectors starting at 0x80000000&lt;BR /&gt;Flash Driver V.2 startup failed - rc Ef(58): Flash Driver describes no sectors at its base address&lt;BR /&gt;chip initialization failed - Ef(58): Flash Driver describes no sectors at its base address&lt;BR /&gt;failed to initialize flash driver MCXN9xx_SFDP_FlexSPI.cfx&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Is there any setting or anything I need to do?&lt;/P&gt;&lt;P&gt;I would appreciate your reply.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 05 Mar 2025 05:44:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2055980#M2589</guid>
      <dc:creator>takagi_y</dc:creator>
      <dc:date>2025-03-05T05:44:19Z</dc:date>
    </item>
    <item>
      <title>Re: Writing QSPI Flash on MCXN947 board.</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2056203#M2591</link>
      <description>&lt;P&gt;As additional information, we would like to inform you of what we did to implement XIP processing from the demo project you contacted us about to the project for this board.&lt;/P&gt;&lt;P&gt;- Copy the following files.&lt;BR /&gt;&amp;nbsp; source\mcxn_flexspi_nor_config.c&lt;BR /&gt;&amp;nbsp; source\mcxn_flexspi_nor_config.h&lt;BR /&gt;&amp;nbsp; linkscripts\rodata.ldt&lt;BR /&gt;&amp;nbsp; linkscripts\text.ldt&lt;/P&gt;&lt;P&gt;- Rewrite to "bootfromflexspi.bin" using blhost.&lt;/P&gt;&lt;P&gt;- Change the settings of the Memory Configuration editor.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="image.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/326825iB59CC573151030E9/image-size/medium?v=v2&amp;amp;px=400" role="button" title="image.png" alt="image.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;I would appreciate your reply.&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 05 Mar 2025 10:20:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2056203#M2591</guid>
      <dc:creator>takagi_y</dc:creator>
      <dc:date>2025-03-05T10:20:57Z</dc:date>
    </item>
    <item>
      <title>Re: Writing QSPI Flash on MCXN947 board.</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2056764#M2596</link>
      <description>&lt;P&gt;HI&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/247126"&gt;@takagi_y&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;"&lt;SPAN&gt;I tried to write to this board using the writing method for FRDM-MCXN947 as a reference, but an error occurred.&lt;/SPAN&gt;"&lt;/P&gt;
&lt;P&gt;You change to another board.&lt;/P&gt;
&lt;P&gt;Did you try the same method but not succeed？&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Harry&lt;/P&gt;</description>
      <pubDate>Thu, 06 Mar 2025 06:24:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2056764#M2596</guid>
      <dc:creator>Harry_Zhang</dc:creator>
      <dc:date>2025-03-06T06:24:42Z</dc:date>
    </item>
    <item>
      <title>Re: Writing QSPI Flash on MCXN947 board.</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2056933#M2599</link>
      <description>&lt;P&gt;Thank you for your reply.&lt;/P&gt;&lt;P&gt;I modified the project with reference to the demo program of FRDM-MCXN947 and confirmed writing from IDE.&lt;BR /&gt;The procedure is as written yesterday under "As additional information...".&lt;/P&gt;&lt;P&gt;My board uses MX25L3233F for Flash, so I built an example of CMSIS-DAP Flash Drivers and checked it.&lt;/P&gt;&lt;P&gt;First, I used the one I built without any modifications and wrote it from the IDE. (CONFIG_OPTION0=0xC0000001)&lt;BR /&gt;As a result, the following was displayed on the console and writing was not performed.&lt;/P&gt;&lt;TABLE border="1" width="100%"&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD width="100%"&gt;&lt;P&gt;MCUXpresso IDE RedlinkMulti Driver v24.9 (Sep 19 2024 19:34:05 - crt_emu_cm_redlink build 802)&lt;/P&gt;&lt;P&gt;Found chip XML file in C:/WorkSpace/MCUX/MCUXpressoIDE_24.9.25/NX-N947/frdmmcxn947_hello_world_qspi_xip/Debug\MCXN947.xml&lt;/P&gt;&lt;P&gt;( 5) Remote configuration complete&lt;/P&gt;&lt;P&gt;Reconnected to existing LinkServer process.&lt;/P&gt;&lt;P&gt;Probe Firmware: MCU-LINK (r0FF) CMSIS-DAP V3.153 (NXP Semiconductors)&lt;/P&gt;&lt;P&gt;Serial Number: VUDADS0NIE0ZM&lt;/P&gt;&lt;P&gt;VID:PID: 1FC9:0143&lt;/P&gt;&lt;P&gt;USB Path: 0001:0008:00&lt;/P&gt;&lt;P&gt;Using memory from core 0 after searching for a good core&lt;/P&gt;&lt;P&gt;processor is in secure mode&lt;/P&gt;&lt;P&gt;debug interface type = CoreSight DP (DAP DP ID 6BA02477) over SWD TAP 0&lt;/P&gt;&lt;P&gt;processor type = Cortex-M33 (CPU ID 00000D21) on DAP AP 0&lt;/P&gt;&lt;P&gt;number of h/w breakpoints = 8&lt;/P&gt;&lt;P&gt;number of flash patches = 0&lt;/P&gt;&lt;P&gt;number of h/w watchpoints = 4&lt;/P&gt;&lt;P&gt;Probe(0): Connected&amp;amp;Reset. DpID: 6BA02477. CpuID: 00000D21. Info: &amp;lt;None&amp;gt;&lt;/P&gt;&lt;P&gt;Debug protocol: SWD. RTCK: Disabled. Vector catch: Disabled.&lt;/P&gt;&lt;P&gt;Content of CoreSight Debug ROM(s):&lt;/P&gt;&lt;P&gt;RBASE E00FE000: CID B105100D PID 0000095000 ROM (type 0x1)&lt;/P&gt;&lt;P&gt;ROM 1 E00FF000: CID B105100D PID 04000BB4C9 ROM (type 0x1)&lt;/P&gt;&lt;P&gt;ROM 2 E000E000: CID B105900D PID 04000BBD21 CSt ARM ARMv8-M type 0x0 Misc - Undefined&lt;/P&gt;&lt;P&gt;ROM 2 E0001000: CID B105900D PID 04000BBD21 CSt ARM DWTv2 type 0x0 Misc - Undefined&lt;/P&gt;&lt;P&gt;ROM 2 E0002000: CID B105900D PID 04000BBD21 CSt ARM FPBv2 type 0x0 Misc - Undefined&lt;/P&gt;&lt;P&gt;ROM 2 E0000000: CID B105900D PID 04000BBD21 CSt ARM ITMv2 type 0x43 Trace Source - Bus&lt;/P&gt;&lt;P&gt;ROM 2 E0041000: CID B105900D PID 04002BBD21 CSt ARM ETMv4.0 type 0x13 Trace Source - Core&lt;/P&gt;&lt;P&gt;ROM 2 E0042000: CID B105900D PID 04000BBD21 CSt ARM CTIv2 type 0x14 Debug Control - Trigger, e.g. ECT&lt;/P&gt;&lt;P&gt;ROM 1 E0040000: CID B105900D PID 04000BBD21 CSt type 0x11 Trace Sink - TPIU&lt;/P&gt;&lt;P&gt;ROM 1 E0044000: CID B105900D PID 04003BB908 CSt CSTF type 0x12 Trace Link - Trace funnel/router&lt;/P&gt;&lt;P&gt;ROM 1 E0045000: CID B105900D PID 04001BB961 CSt type 0x21 Trace Sink - ETB&lt;/P&gt;&lt;P&gt;NXP: MCXN947&lt;/P&gt;&lt;P&gt;DAP stride is 1024 bytes (256 words)&lt;/P&gt;&lt;P&gt;Inspected v.2 External Flash Device on SPI using SFDP JEDEC ID MCXN9xx_SFDP_FlexSPI_.cfx&lt;/P&gt;&lt;P&gt;Image 'MCXN9xx_SFDP_FlexSPI Mar 6 2025 17:01:24'&lt;/P&gt;&lt;P&gt;Opening flash driver MCXN9xx_SFDP_FlexSPI_.cfx&lt;/P&gt;&lt;P&gt;VECTRESET requested, but not supported on ARMv8-M CPUs. Using SOFTRESET instead.&lt;/P&gt;&lt;P&gt;Using SOFT reset to run the flash driver&lt;/P&gt;&lt;P&gt;Flash variant 'JEDEC_FlexSPI_Device' detected (0B = at 0x80000000)&lt;/P&gt;&lt;P&gt;driver describes no sectors starting at 0x80000000&lt;/P&gt;&lt;P&gt;Flash Driver V.2 startup failed - rc Ef(58): Flash Driver describes no sectors at its base address&lt;/P&gt;&lt;P&gt;chip initialization failed - Ef(58): Flash Driver describes no sectors at its base address&lt;/P&gt;&lt;P&gt;failed to initialize flash driver MCXN9xx_SFDP_FlexSPI_.cfx&lt;/P&gt;&lt;P&gt;Inspected v.2 External Flash Device on SPI using SFDP JEDEC ID MCXN9xx_SFDP_FlexSPI_.cfx&lt;/P&gt;&lt;P&gt;Image 'MCXN9xx_SFDP_FlexSPI Mar 6 2025 17:01:24'&lt;/P&gt;&lt;P&gt;Opening flash driver MCXN9xx_SFDP_FlexSPI_.cfx&lt;/P&gt;&lt;P&gt;VECTRESET requested, but not supported on ARMv8-M CPUs. Using SOFTRESET instead.&lt;/P&gt;&lt;P&gt;Using SOFT reset to run the flash driver&lt;/P&gt;&lt;P&gt;Flash variant 'JEDEC_FlexSPI_Device' detected (4MB = 64*64K at 0x80000000)&lt;/P&gt;&lt;P&gt;Closing flash driver MCXN9xx_SFDP_FlexSPI_.cfx&lt;/P&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;P&gt;&lt;BR /&gt;Next, I changed the setting value used in the SEC tool (CONFIG_OPTION0=0xC0000405) and checked, but writing was not performed here either.&lt;BR /&gt;(You can write with the SEC tool.)&lt;BR /&gt;The following is the console display at that time.&lt;/P&gt;&lt;TABLE border="1" width="100%"&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD width="100%"&gt;&lt;P&gt;MCUXpresso IDE RedlinkMulti Driver v24.9 (Sep 19 2024 19:34:05 - crt_emu_cm_redlink build 802)&lt;/P&gt;&lt;P&gt;Found chip XML file in C:/WorkSpace/MCUX/MCUXpressoIDE_24.9.25/NX-N947/NX-N947_ledblinky/frdmmcxn947_led_blinky/Debug_NoRAM\MCXN947.xml&lt;/P&gt;&lt;P&gt;( 5) Remote configuration complete&lt;/P&gt;&lt;P&gt;Reconnected to existing LinkServer process.&lt;/P&gt;&lt;P&gt;Probe Firmware: MCU-LINK (r0FF) CMSIS-DAP V3.153 (NXP Semiconductors)&lt;/P&gt;&lt;P&gt;Serial Number: VUDADS0NIE0ZM&lt;/P&gt;&lt;P&gt;VID:PID: 1FC9:0143&lt;/P&gt;&lt;P&gt;USB Path: 0001:0008:00&lt;/P&gt;&lt;P&gt;Using memory from core 0 after searching for a good core&lt;/P&gt;&lt;P&gt;( 30) Emulator Connected&lt;/P&gt;&lt;P&gt;processor is in secure mode&lt;/P&gt;&lt;P&gt;debug interface type = CoreSight DP (DAP DP ID 6BA02477) over SWD TAP 0&lt;/P&gt;&lt;P&gt;processor type = Cortex-M33 (CPU ID 00000D21) on DAP AP 0&lt;/P&gt;&lt;P&gt;number of h/w breakpoints = 8&lt;/P&gt;&lt;P&gt;number of flash patches = 0&lt;/P&gt;&lt;P&gt;number of h/w watchpoints = 4&lt;/P&gt;&lt;P&gt;Probe(0): Connected&amp;amp;Reset. DpID: 6BA02477. CpuID: 00000D21. Info: &amp;lt;None&amp;gt;&lt;/P&gt;&lt;P&gt;Debug protocol: SWD. RTCK: Disabled. Vector catch: Disabled.&lt;/P&gt;&lt;P&gt;Content of CoreSight Debug ROM(s):&lt;/P&gt;&lt;P&gt;RBASE E00FE000: CID B105100D PID 0000095000 ROM (type 0x1)&lt;/P&gt;&lt;P&gt;ROM 1 E00FF000: CID B105100D PID 04000BB4C9 ROM (type 0x1)&lt;/P&gt;&lt;P&gt;ROM 2 E000E000: CID B105900D PID 04000BBD21 CSt ARM ARMv8-M type 0x0 Misc - Undefined&lt;/P&gt;&lt;P&gt;ROM 2 E0001000: CID B105900D PID 04000BBD21 CSt ARM DWTv2 type 0x0 Misc - Undefined&lt;/P&gt;&lt;P&gt;ROM 2 E0002000: CID B105900D PID 04000BBD21 CSt ARM FPBv2 type 0x0 Misc - Undefined&lt;/P&gt;&lt;P&gt;ROM 2 E0000000: CID B105900D PID 04000BBD21 CSt ARM ITMv2 type 0x43 Trace Source - Bus&lt;/P&gt;&lt;P&gt;ROM 2 E0041000: CID B105900D PID 04002BBD21 CSt ARM ETMv4.0 type 0x13 Trace Source - Core&lt;/P&gt;&lt;P&gt;ROM 2 E0042000: CID B105900D PID 04000BBD21 CSt ARM CTIv2 type 0x14 Debug Control - Trigger, e.g. ECT&lt;/P&gt;&lt;P&gt;ROM 1 E0040000: CID B105900D PID 04000BBD21 CSt type 0x11 Trace Sink - TPIU&lt;/P&gt;&lt;P&gt;ROM 1 E0044000: CID B105900D PID 04003BB908 CSt CSTF type 0x12 Trace Link - Trace funnel/router&lt;/P&gt;&lt;P&gt;ROM 1 E0045000: CID B105900D PID 04001BB961 CSt type 0x21 Trace Sink - ETB&lt;/P&gt;&lt;P&gt;NXP: MCXN947&lt;/P&gt;&lt;P&gt;DAP stride is 1024 bytes (256 words)&lt;/P&gt;&lt;P&gt;Inspected v.2 External Flash Device on SPI using SFDP JEDEC ID MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx&lt;/P&gt;&lt;P&gt;Image 'MCXN9xx_SFDP_FlexSPI Mar 6 2025 18:26:01'&lt;/P&gt;&lt;P&gt;Opening flash driver MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx&lt;/P&gt;&lt;P&gt;VECTRESET requested, but not supported on ARMv8-M CPUs. Using SOFTRESET instead.&lt;/P&gt;&lt;P&gt;Using SOFT reset to run the flash driver&lt;/P&gt;&lt;P&gt;Driver V.2 dynamic startup failed - driver Init provided no flash parameters&lt;/P&gt;&lt;P&gt;driver describes no sectors starting at 0x80000000&lt;/P&gt;&lt;P&gt;Flash Driver V.2 startup failed - rc Ef(58): Flash Driver describes no sectors at its base address&lt;/P&gt;&lt;P&gt;chip initialization failed - Ef(58): Flash Driver describes no sectors at its base address&lt;/P&gt;&lt;P&gt;failed to initialize flash driver MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx&lt;/P&gt;&lt;P&gt;Inspected v.2 External Flash Device on SPI using SFDP JEDEC ID MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx&lt;/P&gt;&lt;P&gt;Image 'MCXN9xx_SFDP_FlexSPI Mar 6 2025 18:26:01'&lt;/P&gt;&lt;P&gt;Opening flash driver MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx&lt;/P&gt;&lt;P&gt;VECTRESET requested, but not supported on ARMv8-M CPUs. Using SOFTRESET instead.&lt;/P&gt;&lt;P&gt;Using SOFT reset to run the flash driver&lt;/P&gt;&lt;P&gt;Driver V.2 dynamic startup failed - driver Init provided no flash parameters&lt;/P&gt;&lt;P&gt;driver describes no sectors starting at 0x80000000&lt;/P&gt;&lt;P&gt;Flash Driver V.2 startup failed - rc Ef(58): Flash Driver describes no sectors at its base address&lt;/P&gt;&lt;P&gt;chip initialization failed - Ef(58): Flash Driver describes no sectors at its base address&lt;/P&gt;&lt;P&gt;failed to initialize flash driver MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx&lt;/P&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;P&gt;&lt;BR /&gt;Is it necessary to change anything other than CONFIG_OPTION0 for MX25L3233F?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;</description>
      <pubDate>Thu, 06 Mar 2025 09:50:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2056933#M2599</guid>
      <dc:creator>takagi_y</dc:creator>
      <dc:date>2025-03-06T09:50:05Z</dc:date>
    </item>
    <item>
      <title>Re: Writing QSPI Flash on MCXN947 board.</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2057744#M2607</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/247126"&gt;@takagi_y&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;On FRDM-MCXN947, the Qflash is&amp;nbsp;W25Q64JVSSIQ.&lt;/P&gt;
&lt;P&gt;On your customer board, the qflash is&amp;nbsp;MX25L3233F.&lt;/P&gt;
&lt;P&gt;So you need to change the&amp;nbsp;Flash burning algorithm.&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Such as MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;And in the mcxn_flexspi_nor_config.c&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Change the LUT&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Snipaste_2025-03-07_18-01-29.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/327151i410610CB2C63825B/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Snipaste_2025-03-07_18-01-29.png" alt="Snipaste_2025-03-07_18-01-29.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Harry&lt;/P&gt;</description>
      <pubDate>Fri, 07 Mar 2025 10:02:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2057744#M2607</guid>
      <dc:creator>Harry_Zhang</dc:creator>
      <dc:date>2025-03-07T10:02:49Z</dc:date>
    </item>
    <item>
      <title>Re: Writing QSPI Flash on MCXN947 board.</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2058562#M2629</link>
      <description>&lt;P&gt;Thank you for your reply.&lt;/P&gt;&lt;P&gt;I compared the data sheets for W25Q64JVSSIQ and MX25L3233F and confirmed that the LUT contents are the same.&lt;/P&gt;&lt;P&gt;&amp;gt; So you need to change the Flash burning algorithm.&lt;BR /&gt;&amp;gt; Such as MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx&lt;/P&gt;&lt;P&gt;Does the above mean that you need to change the code other than CONFIG_OPTION0 and CONFIG_OPTION1 in MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx?&lt;/P&gt;&lt;P&gt;Or does it mean that there are other files that need to be modified besides MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx?&lt;/P&gt;&lt;P&gt;If other files need to be modified, could you please let me know the files?&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;</description>
      <pubDate>Mon, 10 Mar 2025 07:51:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2058562#M2629</guid>
      <dc:creator>takagi_y</dc:creator>
      <dc:date>2025-03-10T07:51:21Z</dc:date>
    </item>
    <item>
      <title>Re: Writing QSPI Flash on MCXN947 board.</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2062145#M2678</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/247126"&gt;@takagi_y&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Apart from &lt;SPAN&gt;MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx&lt;/SPAN&gt; and &lt;SPAN&gt;mcxn_flexspi_nor_config.c&lt;/SPAN&gt;, there are no other files that need to be modified.&lt;/P&gt;
&lt;P&gt;"&lt;SPAN&gt;I compared the data sheets for W25Q64JVSSIQ and MX25L3233F and confirmed that the LUT contents are the same.&lt;/SPAN&gt;"&lt;/P&gt;
&lt;P&gt;No, they are different.&lt;/P&gt;
&lt;P&gt;You can refer to the flexspi_polling example, it includes the LUT of&amp;nbsp;&lt;SPAN&gt;W25Q64JVSSIQ and MX25L3233F.&lt;/SPAN&gt;&lt;/P&gt;
&lt;LI-CODE lang="markup"&gt;#if EXAMPLE_FLASH_TYPE == FLASH_W25Q64
/* W25Q64JVSSIQ */
const uint32_t customLUTOctalMode[CUSTOM_LUT_LENGTH] = {
    /* Read data */
    [4 * NOR_CMD_LUT_SEQ_IDX_READ] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xEB, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 0x18),
    [4 * NOR_CMD_LUT_SEQ_IDX_READ + 1] = FLEXSPI_LUT_SEQ(
        kFLEXSPI_Command_MODE8_SDR, kFLEXSPI_4PAD, 0xF0, kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 0x04),
    [4 * NOR_CMD_LUT_SEQ_IDX_READ + 2] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x00, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),

    /* Read status register */
    [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x05, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x00),

    /* Write enable */
    [4 * NOR_CMD_LUT_SEQ_IDX_WRITEENABLE] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x06, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),

    /* Write enable */
    [4 * NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_OPI] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x06, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),

    /* Read ID */
    [4 * NOR_CMD_LUT_SEQ_IDX_READID_OPI] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x9F, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x00),

    /* Sector erase */
    [4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x20, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),

    /* Chip erase */
    [4 * NOR_CMD_LUT_SEQ_IDX_CHIPERASE] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x60, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),

    /* Page program */
    [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x32, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
    [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 1] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x00, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),

    /* Enter Quad mode */
    [4 * NOR_CMD_LUT_SEQ_IDX_ENTEROPI] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x05, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x00),

    /*  Dummy write, do nothing when AHB write command is triggered. */
    [4 * NOR_CMD_LUT_SEQ_IDX_WRITE] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),

    /*  Read status register using Quad mode */
    [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS_OPI] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x05, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x00),

};
#endif

#if EXAMPLE_FLASH_TYPE == FLASH_MT35XU512
/* MT35XU512ABA1G12 */
const uint32_t customLUTOctalMode[CUSTOM_LUT_LENGTH] = {

    /*  OPI DDR read */
    [4 * NOR_CMD_LUT_SEQ_IDX_READ] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xCC, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xCC),
    [4 * NOR_CMD_LUT_SEQ_IDX_READ + 1] = FLEXSPI_LUT_SEQ(
        kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_8PAD, 0x0D),
    [4 * NOR_CMD_LUT_SEQ_IDX_READ + 2] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),

    /* Read status register */
    [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x05, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x00),

    /* Write Enable */
    [4 * NOR_CMD_LUT_SEQ_IDX_WRITEENABLE] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x06, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),

    /* Read ID under octal mode */
    [4 * NOR_CMD_LUT_SEQ_IDX_READID_OPI] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x9F, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x9F),
    [4 * NOR_CMD_LUT_SEQ_IDX_READID_OPI + 1] = FLEXSPI_LUT_SEQ(
        kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x00),

    /*  Write Enable */
    [4 * NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_OPI] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x06, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x06),

    /*  Erase Sector */
    [4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20),
    [4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR + 1] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),

    /*  Erase Chip */
    [4 * NOR_CMD_LUT_SEQ_IDX_CHIPERASE] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x60, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x60),

    /*  Program */
    [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x8E, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x8E),
    [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 1] = FLEXSPI_LUT_SEQ(
        kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x00),

    /* Enter OPI mode */
    [4 * NOR_CMD_LUT_SEQ_IDX_ENTEROPI] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x81, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
    [4 * NOR_CMD_LUT_SEQ_IDX_ENTEROPI + 1] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x00, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),

    /*  Dummy write, do nothing when AHB write command is triggered. */
    [4 * NOR_CMD_LUT_SEQ_IDX_WRITE] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),

    /*  Read status register using Octal DDR read */
    [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS_OPI] =
        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
    [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS_OPI + 1] = FLEXSPI_LUT_SEQ(
        kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x00),
};
#endif
&lt;/LI-CODE&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Harry&lt;/P&gt;</description>
      <pubDate>Fri, 14 Mar 2025 14:39:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2062145#M2678</guid>
      <dc:creator>Harry_Zhang</dc:creator>
      <dc:date>2025-03-14T14:39:23Z</dc:date>
    </item>
    <item>
      <title>Re: Writing QSPI Flash on MCXN947 board.</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2062597#M2689</link>
      <description>&lt;P&gt;Thank you for your reply.&lt;/P&gt;&lt;P&gt;I have checked the example you provided.&lt;BR /&gt;The Flash I want to use is MX25L3233F.&lt;BR /&gt;The example you provided is for MT35XU512ABA, which is a different model number.&lt;/P&gt;&lt;P&gt;The following is an excerpt of the MX25L3233F command, which is the same as the MT35XU512ABA command.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="image.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/328327i94C86C7AF2FA589B/image-size/medium?v=v2&amp;amp;px=400" role="button" title="image.png" alt="image.png" /&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="image.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/328328i698FE86060F7501C/image-size/medium?v=v2&amp;amp;px=400" role="button" title="image.png" alt="image.png" /&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="image.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/328329iD674305B2D9D8BB1/image-size/medium?v=v2&amp;amp;px=400" role="button" title="image.png" alt="image.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;It is MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx, but do I need to make any changes other than to FlashConfig.h?&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;</description>
      <pubDate>Mon, 17 Mar 2025 01:01:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2062597#M2689</guid>
      <dc:creator>takagi_y</dc:creator>
      <dc:date>2025-03-17T01:01:16Z</dc:date>
    </item>
    <item>
      <title>Re: Writing QSPI Flash on MCXN947 board.</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2063601#M2709</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/247126"&gt;@takagi_y&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Apart from MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx and &lt;SPAN&gt;&amp;nbsp;FlashConfig.h&lt;/SPAN&gt;, there are no other files that need to be modified.&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Harry&lt;/P&gt;</description>
      <pubDate>Tue, 18 Mar 2025 08:45:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2063601#M2709</guid>
      <dc:creator>Harry_Zhang</dc:creator>
      <dc:date>2025-03-18T08:45:25Z</dc:date>
    </item>
    <item>
      <title>Re: Writing QSPI Flash on MCXN947 board.</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2066272#M2739</link>
      <description>&lt;P&gt;Thank you for your reply.&lt;/P&gt;&lt;P&gt;I have only modified the two files you mentioned, but the error still occurs.&lt;/P&gt;&lt;P&gt;I will upload the files I am using and the error message.&lt;/P&gt;&lt;P&gt;I cannot identify the reason why the Flash Driver V2 fails to start, so please give me some advice.&lt;/P&gt;&lt;P&gt;mcxn_flexspi_nor_config.c&lt;BR /&gt;In this file, the value of sflashA1Size has been changed from 8M to 4M.&lt;/P&gt;&lt;TABLE border="1" width="100%"&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD width="100%"&gt;&lt;P&gt;/*&lt;BR /&gt;* Copyright 2018-2022 NXP&lt;BR /&gt;* All rights reserved.&lt;BR /&gt;*&lt;BR /&gt;* SPDX-License-Identifier: BSD-3-Clause&lt;BR /&gt;*/&lt;/P&gt;&lt;P&gt;#include "mcxn_flexspi_nor_config.h"&lt;/P&gt;&lt;P&gt;/* Component ID definition, used by tools. */&lt;BR /&gt;#ifndef FSL_COMPONENT_ID&lt;BR /&gt;#define FSL_COMPONENT_ID "platform.drivers.xip_board"&lt;BR /&gt;#endif&lt;/P&gt;&lt;P&gt;/*******************************************************************************&lt;BR /&gt;* Code&lt;BR /&gt;******************************************************************************/&lt;/P&gt;&lt;P&gt;#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)&lt;BR /&gt;__attribute__((section(".flexspi_fcb"), used))&lt;BR /&gt;#elif defined(__ICCARM__)&lt;BR /&gt;#pragma location = ".flexspi_fcb"&lt;BR /&gt;#endif&lt;/P&gt;&lt;P&gt;#ifndef FLEXSPI_USE_CUSTOM_FCB&lt;BR /&gt;#define FLEXSPI_USE_CUSTOM_FCB (0)&lt;BR /&gt;#endif&lt;/P&gt;&lt;P&gt;#if FLEXSPI_USE_CUSTOM_FCB&lt;BR /&gt;/* FCB for W25Q64 */&lt;BR /&gt;const uint8_t CUSTOM_FCB[] = {&lt;BR /&gt;0x46, 0x43, 0x46, 0x42, 0x00, 0x04, 0x01, 0x56, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00,&lt;BR /&gt;0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,&lt;BR /&gt;0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,&lt;BR /&gt;0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,&lt;BR /&gt;0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,&lt;BR /&gt;0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,&lt;BR /&gt;0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xeb, 0x04, 0x18, 0x0a, 0x06,&lt;BR /&gt;0x32, 0x04, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x04, 0x04, 0x24, 0x00, 0x00, 0x00, 0x00,&lt;BR /&gt;0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,&lt;BR /&gt;0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,&lt;BR /&gt;0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,&lt;BR /&gt;0x04, 0x18, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,&lt;BR /&gt;0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,&lt;BR /&gt;0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd8, 0x04, 0x18, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,&lt;BR /&gt;0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x04, 0x18, 0x08, 0x04, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,&lt;BR /&gt;0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,&lt;BR /&gt;0x60, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,&lt;BR /&gt;0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,&lt;BR /&gt;0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,&lt;BR /&gt;0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,&lt;BR /&gt;0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,&lt;BR /&gt;0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,&lt;BR /&gt;0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,&lt;BR /&gt;0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,&lt;BR /&gt;0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,&lt;BR /&gt;0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,&lt;BR /&gt;0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};&lt;BR /&gt;#else&lt;/P&gt;&lt;P&gt;/* FCB for W25Q64 */&lt;BR /&gt;const flexspi_nor_config_t qspiflash_config = {&lt;BR /&gt;.memConfig =&lt;BR /&gt;{&lt;BR /&gt;.tag = FLEXSPI_CFG_BLK_TAG,&lt;BR /&gt;.version = FLEXSPI_CFG_BLK_VERSION,&lt;BR /&gt;.readSampleClksrc=kFlexSPIReadSampleClk_LoopbackFromDqsPad,&lt;BR /&gt;.csHoldTime = 3u,&lt;BR /&gt;.csSetupTime = 3u,&lt;BR /&gt;// Enable DDR mode, Wordaddassable, Safe configuration, Differential clock&lt;BR /&gt;.controllerMiscOption = (1u &amp;lt;&amp;lt; kFlexSpiMiscOffset_SafeConfigFreqEnable),&lt;BR /&gt;.deviceType = kFlexSpiDeviceType_SerialNOR,&lt;BR /&gt;.sflashPadType = kSerialFlash_4Pads,&lt;BR /&gt;.serialClkFreq = kFlexSpiSerialClk_75MHz,&lt;BR /&gt;.sflashA1Size = 4u * 1024u * 1024u,&lt;BR /&gt;.lookupTable =&lt;BR /&gt;{&lt;BR /&gt;// Read LUTs&lt;BR /&gt;[0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),&lt;BR /&gt;[1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),&lt;/P&gt;&lt;P&gt;// Read Status LUTs&lt;BR /&gt;[4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04),&lt;/P&gt;&lt;P&gt;// Write Enable LUTs&lt;BR /&gt;[4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0x0),&lt;/P&gt;&lt;P&gt;// Erase Sector LUTs&lt;BR /&gt;[4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20, RADDR_SDR, FLEXSPI_1PAD, 0x18),&lt;/P&gt;&lt;P&gt;// Erase Block LUTs&lt;BR /&gt;[4 * 8 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8, RADDR_SDR, FLEXSPI_1PAD, 0x18),&lt;/P&gt;&lt;P&gt;// Pape Program LUTs&lt;BR /&gt;[4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02, RADDR_SDR, FLEXSPI_1PAD, 0x18),&lt;BR /&gt;[4 * 9 + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0),&lt;/P&gt;&lt;P&gt;// Erase Chip LUTs&lt;BR /&gt;[4 * 11 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP, FLEXSPI_1PAD, 0x0),&lt;BR /&gt;},&lt;BR /&gt;},&lt;BR /&gt;.pageSize = 256u,&lt;BR /&gt;.sectorSize = 4u * 1024u,&lt;BR /&gt;.ipcmdSerialClkFreq = 1u,&lt;BR /&gt;.blockSize = 64u * 1024u,&lt;BR /&gt;.isUniformBlockSize = false,&lt;BR /&gt;};&lt;BR /&gt;#endif&lt;/P&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;FlashConfig.h&lt;BR /&gt;I created four different versions of this file with different values ​​for CONFIG_OPTION0. (0xC0000001, 0xC0000405, 0xC0000401, 0xC0000101)&lt;BR /&gt;I have used each one to check.&lt;/P&gt;&lt;TABLE border="1" width="100%"&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD width="100%"&gt;&lt;P&gt;//*****************************************************************************&lt;BR /&gt;// FlashConfig.h&lt;BR /&gt;// MCUXpresso IDE Flash driver&lt;BR /&gt;// Config file for MCXN9xx FlexSPI driver&lt;BR /&gt;//*****************************************************************************&lt;BR /&gt;//&lt;BR /&gt;// Copyright 2022-2024 NXP&lt;BR /&gt;//&lt;BR /&gt;// SPDX-License-Identifier: BSD-3-Clause&lt;BR /&gt;//*****************************************************************************&lt;/P&gt;&lt;P&gt;#ifndef FLASHCONFIG_H_&lt;BR /&gt;#define FLASHCONFIG_H_&lt;/P&gt;&lt;P&gt;#include "fsl_flexspi_nor_flash.h"&lt;/P&gt;&lt;P&gt;extern flexspi_nor_config_t flashConfig;&lt;/P&gt;&lt;P&gt;#if defined (DEBUG)&lt;BR /&gt;#define MCXN9xx_SFDP_FlexSPI&lt;BR /&gt;#endif&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;// MCX N1xNxxx Reference Manual - 15.4.2 FlexSPI NOR Configuration Option Block&lt;/P&gt;&lt;P&gt;#if defined (MCXN9xx_SFDP_FlexSPI) || defined (MCXN9xx_SFDP_FlexSPI_S)&lt;BR /&gt;/*&lt;BR /&gt;* 0xC : tag&lt;BR /&gt;* 0 : option_size (0 = option1 not specified)&lt;BR /&gt;* 0 : device_type (0 = Read SFDP for SDR commands)&lt;BR /&gt;* 0 : query_pads (0 = 1 data pad during query)&lt;BR /&gt;* 0 : cmd_pads (0 = 1 data pad during flash access)&lt;BR /&gt;* 0 : quad_mode_setting (0 = not configured)&lt;BR /&gt;* 0 : misc_mode&lt;BR /&gt;* 1 : max_freq (0 = Don't change FlexSPI clock setting)&lt;BR /&gt;*/&lt;BR /&gt;#define CONFIG_OPTION0 0xC0000001&lt;BR /&gt;//#define CONFIG_OPTION0 0xC0000405&lt;BR /&gt;//#define CONFIG_OPTION0 0xC0000401&lt;BR /&gt;//#define CONFIG_OPTION0 0xC0000101&lt;/P&gt;&lt;P&gt;/*&lt;BR /&gt;* 0x0 : Single Flash connected to Port A&lt;BR /&gt;*/&lt;BR /&gt;#define CONFIG_OPTION1 0x00000000&lt;/P&gt;&lt;P&gt;#endif&lt;/P&gt;&lt;P&gt;// =====================================&lt;BR /&gt;// Flash Base Address Information&lt;BR /&gt;// =====================================&lt;BR /&gt;#if defined (MCXN9xx_SFDP_FlexSPI_S)&lt;BR /&gt;#define USE_SECURE_FLASHADDR&lt;BR /&gt;#define FLASH_BASE_ADDR 0x90000000&lt;BR /&gt;#else&lt;BR /&gt;#define FLASH_BASE_ADDR 0x80000000&lt;BR /&gt;#endif&lt;/P&gt;&lt;P&gt;#endif /* FLASHCONFIG_H_ */&lt;/P&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;When 0xC0000001 is used for CONFIG_OPTION0, the following Console A is displayed on the Console, and when not, Console B is displayed.&lt;/P&gt;&lt;P&gt;Console A&lt;/P&gt;&lt;TABLE border="1" width="100%"&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD width="100%"&gt;MCUXpresso IDE RedlinkMulti Driver v24.9 (Sep 19 2024 19:34:05 - crt_emu_cm_redlink build 802)&lt;BR /&gt;Found chip XML file in C:/WorkSpace/MCUX/MCUXpressoIDE_24.9.25/NX-N947/NX-N947_ledblinky/frdmmcxn947_led_blinky/Debug_NoRAM\MCXN947.xml&lt;BR /&gt;( 5) Remote configuration complete&lt;BR /&gt;Reconnected to existing LinkServer process.&lt;BR /&gt;Probe Firmware: MCU-LINK (r0FF) CMSIS-DAP V3.153 (NXP Semiconductors)&lt;BR /&gt;Serial Number: VUDADS0NIE0ZM&lt;BR /&gt;VID:PID: 1FC9:0143&lt;BR /&gt;USB Path: 0001:0003:00&lt;BR /&gt;Using memory from core 0 after searching for a good core&lt;BR /&gt;processor is in secure mode&lt;BR /&gt;debug interface type = CoreSight DP (DAP DP ID 6BA02477) over SWD TAP 0&lt;BR /&gt;processor type = Cortex-M33 (CPU ID 00000D21) on DAP AP 0&lt;BR /&gt;number of h/w breakpoints = 8&lt;BR /&gt;number of flash patches = 0&lt;BR /&gt;number of h/w watchpoints = 4&lt;BR /&gt;Probe(0): Connected&amp;amp;Reset. DpID: 6BA02477. CpuID: 00000D21. Info: &amp;lt;None&amp;gt;&lt;BR /&gt;Debug protocol: SWD. RTCK: Disabled. Vector catch: Disabled.&lt;BR /&gt;Content of CoreSight Debug ROM(s):&lt;BR /&gt;RBASE E00FE000: CID B105100D PID 0000095000 ROM (type 0x1)&lt;BR /&gt;ROM 1 E00FF000: CID B105100D PID 04000BB4C9 ROM (type 0x1)&lt;BR /&gt;ROM 2 E000E000: CID B105900D PID 04000BBD21 CSt ARM ARMv8-M type 0x0 Misc - Undefined&lt;BR /&gt;ROM 2 E0001000: CID B105900D PID 04000BBD21 CSt ARM DWTv2 type 0x0 Misc - Undefined&lt;BR /&gt;ROM 2 E0002000: CID B105900D PID 04000BBD21 CSt ARM FPBv2 type 0x0 Misc - Undefined&lt;BR /&gt;ROM 2 E0000000: CID B105900D PID 04000BBD21 CSt ARM ITMv2 type 0x43 Trace Source - Bus&lt;BR /&gt;ROM 2 E0041000: CID B105900D PID 04002BBD21 CSt ARM ETMv4.0 type 0x13 Trace Source - Core&lt;BR /&gt;ROM 2 E0042000: CID B105900D PID 04000BBD21 CSt ARM CTIv2 type 0x14 Debug Control - Trigger, e.g. ECT&lt;BR /&gt;ROM 1 E0040000: CID B105900D PID 04000BBD21 CSt type 0x11 Trace Sink - TPIU&lt;BR /&gt;ROM 1 E0044000: CID B105900D PID 04003BB908 CSt CSTF type 0x12 Trace Link - Trace funnel/router&lt;BR /&gt;ROM 1 E0045000: CID B105900D PID 04001BB961 CSt type 0x21 Trace Sink - ETB&lt;BR /&gt;NXP: MCXN947&lt;BR /&gt;DAP stride is 1024 bytes (256 words)&lt;BR /&gt;Inspected v.2 External Flash Device on SPI using SFDP JEDEC ID MCXN9xx_SFDP_FlexSPI_0xC0000001.cfx&lt;BR /&gt;Image 'MCXN9xx_SFDP_FlexSPI Mar 21 2025 14:26:16'&lt;BR /&gt;Opening flash driver MCXN9xx_SFDP_FlexSPI_0xC0000001.cfx&lt;BR /&gt;VECTRESET requested, but not supported on ARMv8-M CPUs. Using SOFTRESET instead.&lt;BR /&gt;Using SOFT reset to run the flash driver&lt;BR /&gt;Flash variant 'JEDEC_FlexSPI_Device' detected (0B = at 0x80000000)&lt;BR /&gt;driver describes no sectors starting at 0x80000000&lt;BR /&gt;Flash Driver V.2 startup failed - rc Ef(58): Flash Driver describes no sectors at its base address&lt;BR /&gt;chip initialization failed - Ef(58): Flash Driver describes no sectors at its base address&lt;BR /&gt;failed to initialize flash driver MCXN9xx_SFDP_FlexSPI_0xC0000001.cfx&lt;BR /&gt;Inspected v.2 External Flash Device on SPI using SFDP JEDEC ID MCXN9xx_SFDP_FlexSPI_0xC0000001.cfx&lt;BR /&gt;Image 'MCXN9xx_SFDP_FlexSPI Mar 21 2025 14:26:16'&lt;BR /&gt;Opening flash driver MCXN9xx_SFDP_FlexSPI_0xC0000001.cfx&lt;BR /&gt;VECTRESET requested, but not supported on ARMv8-M CPUs. Using SOFTRESET instead.&lt;BR /&gt;Using SOFT reset to run the flash driver&lt;BR /&gt;Flash variant 'JEDEC_FlexSPI_Device' detected (4MB = 64*64K at 0x80000000)&lt;BR /&gt;Closing flash driver MCXN9xx_SFDP_FlexSPI_0xC0000001.cfx&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Console B&lt;/P&gt;&lt;TABLE border="1" width="100%"&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD width="100%"&gt;MCUXpresso IDE RedlinkMulti Driver v24.9 (Sep 19 2024 19:34:05 - crt_emu_cm_redlink build 802)&lt;BR /&gt;Found chip XML file in C:/WorkSpace/MCUX/MCUXpressoIDE_24.9.25/NX-N947/NX-N947_ledblinky/frdmmcxn947_led_blinky/Debug_NoRAM\MCXN947.xml&lt;BR /&gt;( 5) Remote configuration complete&lt;BR /&gt;Reconnected to existing LinkServer process.&lt;BR /&gt;Probe Firmware: MCU-LINK (r0FF) CMSIS-DAP V3.153 (NXP Semiconductors)&lt;BR /&gt;Serial Number: VUDADS0NIE0ZM&lt;BR /&gt;VID:PID: 1FC9:0143&lt;BR /&gt;USB Path: 0001:0003:00&lt;BR /&gt;Using memory from core 0 after searching for a good core&lt;BR /&gt;processor is in secure mode&lt;BR /&gt;debug interface type = CoreSight DP (DAP DP ID 6BA02477) over SWD TAP 0&lt;BR /&gt;processor type = Cortex-M33 (CPU ID 00000D21) on DAP AP 0&lt;BR /&gt;number of h/w breakpoints = 8&lt;BR /&gt;number of flash patches = 0&lt;BR /&gt;number of h/w watchpoints = 4&lt;BR /&gt;Probe(0): Connected&amp;amp;Reset. DpID: 6BA02477. CpuID: 00000D21. Info: &amp;lt;None&amp;gt;&lt;BR /&gt;Debug protocol: SWD. RTCK: Disabled. Vector catch: Disabled.&lt;BR /&gt;Content of CoreSight Debug ROM(s):&lt;BR /&gt;RBASE E00FE000: CID B105100D PID 0000095000 ROM (type 0x1)&lt;BR /&gt;ROM 1 E00FF000: CID B105100D PID 04000BB4C9 ROM (type 0x1)&lt;BR /&gt;ROM 2 E000E000: CID B105900D PID 04000BBD21 CSt ARM ARMv8-M type 0x0 Misc - Undefined&lt;BR /&gt;ROM 2 E0001000: CID B105900D PID 04000BBD21 CSt ARM DWTv2 type 0x0 Misc - Undefined&lt;BR /&gt;ROM 2 E0002000: CID B105900D PID 04000BBD21 CSt ARM FPBv2 type 0x0 Misc - Undefined&lt;BR /&gt;ROM 2 E0000000: CID B105900D PID 04000BBD21 CSt ARM ITMv2 type 0x43 Trace Source - Bus&lt;BR /&gt;ROM 2 E0041000: CID B105900D PID 04002BBD21 CSt ARM ETMv4.0 type 0x13 Trace Source - Core&lt;BR /&gt;ROM 2 E0042000: CID B105900D PID 04000BBD21 CSt ARM CTIv2 type 0x14 Debug Control - Trigger, e.g. ECT&lt;BR /&gt;ROM 1 E0040000: CID B105900D PID 04000BBD21 CSt type 0x11 Trace Sink - TPIU&lt;BR /&gt;ROM 1 E0044000: CID B105900D PID 04003BB908 CSt CSTF type 0x12 Trace Link - Trace funnel/router&lt;BR /&gt;ROM 1 E0045000: CID B105900D PID 04001BB961 CSt type 0x21 Trace Sink - ETB&lt;BR /&gt;NXP: MCXN947&lt;BR /&gt;DAP stride is 1024 bytes (256 words)&lt;BR /&gt;Inspected v.2 External Flash Device on SPI using SFDP JEDEC ID MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx&lt;BR /&gt;Image 'MCXN9xx_SFDP_FlexSPI Mar 6 2025 18:26:01'&lt;BR /&gt;Opening flash driver MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx&lt;BR /&gt;VECTRESET requested, but not supported on ARMv8-M CPUs. Using SOFTRESET instead.&lt;BR /&gt;Using SOFT reset to run the flash driver&lt;BR /&gt;Driver V.2 dynamic startup failed - driver Init provided no flash parameters&lt;BR /&gt;driver describes no sectors starting at 0x80000000&lt;BR /&gt;Flash Driver V.2 startup failed - rc Ef(58): Flash Driver describes no sectors at its base address&lt;BR /&gt;chip initialization failed - Ef(58): Flash Driver describes no sectors at its base address&lt;BR /&gt;failed to initialize flash driver MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx&lt;BR /&gt;Inspected v.2 External Flash Device on SPI using SFDP JEDEC ID MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx&lt;BR /&gt;Image 'MCXN9xx_SFDP_FlexSPI Mar 6 2025 18:26:01'&lt;BR /&gt;Opening flash driver MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx&lt;BR /&gt;VECTRESET requested, but not supported on ARMv8-M CPUs. Using SOFTRESET instead.&lt;BR /&gt;Using SOFT reset to run the flash driver&lt;BR /&gt;Driver V.2 dynamic startup failed - driver Init provided no flash parameters&lt;BR /&gt;driver describes no sectors starting at 0x80000000&lt;BR /&gt;Flash Driver V.2 startup failed - rc Ef(58): Flash Driver describes no sectors at its base address&lt;BR /&gt;chip initialization failed - Ef(58): Flash Driver describes no sectors at its base address&lt;BR /&gt;failed to initialize flash driver MCXN9xx_SFDP_FlexSPI_0xC0000405.cfx&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;</description>
      <pubDate>Fri, 21 Mar 2025 10:28:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2066272#M2739</guid>
      <dc:creator>takagi_y</dc:creator>
      <dc:date>2025-03-21T10:28:06Z</dc:date>
    </item>
    <item>
      <title>Re: Writing QSPI Flash on MCXN947 board.</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2067024#M2791</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/247126"&gt;@takagi_y&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Have we considered hardware connectivity issues?&lt;/P&gt;
&lt;P&gt;Are you a custom board？&lt;/P&gt;
&lt;P&gt;If you are a custom board, can you connect this flash to FRDM-MXN947?&lt;/P&gt;
&lt;P&gt;And try again.&lt;/P&gt;
&lt;P&gt;If the flash still cannot work when connected to FRDM-MXN947.&lt;/P&gt;
&lt;P&gt;I will buy this flash and test it.&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Harry&lt;/P&gt;</description>
      <pubDate>Mon, 24 Mar 2025 07:46:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2067024#M2791</guid>
      <dc:creator>Harry_Zhang</dc:creator>
      <dc:date>2025-03-24T07:46:11Z</dc:date>
    </item>
    <item>
      <title>Re: Writing QSPI Flash on MCXN947 board.</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2067611#M2803</link>
      <description>&lt;P&gt;Thank you for your reply.&lt;/P&gt;&lt;P&gt;We will consider your reply.&lt;/P&gt;&lt;P&gt;Also, on my board, FLEXSPI0_A_SS0_b is connected to MX25L3233, but FLEXSPI0_A_SS1_b is connected to PSRAM.&lt;BR /&gt;The same terminal is used for FLEXSPI0_A_SCLK and FLEXSPI0_A_DATA0-3 of the two chips.&lt;BR /&gt;Do you think that this state will affect the writing of the flash?&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;</description>
      <pubDate>Tue, 25 Mar 2025 00:46:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2067611#M2803</guid>
      <dc:creator>takagi_y</dc:creator>
      <dc:date>2025-03-25T00:46:37Z</dc:date>
    </item>
    <item>
      <title>Re: Writing QSPI Flash on MCXN947 board.</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2067631#M2804</link>
      <description>&lt;P&gt;Thank you for your reply.&lt;/P&gt;&lt;P&gt;As you suggested, I replaced the Flash of FRDM-MXN947 with MX25L3233 and checked.&lt;BR /&gt;I was able to write when I used the same mcxn_flexspi_nor_config.c as the one I uploaded the other day and FlashConfig.h with CONFIG_OPTION0 set to 0xC0000101.&lt;/P&gt;&lt;P&gt;However, I cannot write on my board even when I use the same file.&lt;/P&gt;&lt;P&gt;On my board, I use port A in INDIVIDUAL mode, so SS0_b is connected to MX25L3233 and SS1_b is connected to PSRAM, but I wonder if PSRAM is affecting it.&lt;BR /&gt;I have attached a circuit diagram showing the connection of Flash and PSRAM.&lt;BR /&gt;If you have any comments, please give me some advice.&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="N947-FlexSPI.png" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/329590i0027E8D352A7CF05/image-size/large?v=v2&amp;amp;px=999" role="button" title="N947-FlexSPI.png" alt="N947-FlexSPI.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Also, I have set the Memory configuration editor as follows.&lt;BR /&gt;The flash size is set to 0xffff000, but since I'm using a 4MByte product, I think 0x3ff000 is correct.&lt;BR /&gt;Will this size setting affect flash writing?&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="memory_config.bmp" style="width: 554px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/329591i1A0F66904D29EE85/image-size/large?v=v2&amp;amp;px=999" role="button" title="memory_config.bmp" alt="memory_config.bmp" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;</description>
      <pubDate>Tue, 25 Mar 2025 03:07:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2067631#M2804</guid>
      <dc:creator>takagi_y</dc:creator>
      <dc:date>2025-03-25T03:07:09Z</dc:date>
    </item>
    <item>
      <title>Re: Writing QSPI Flash on MCXN947 board.</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2068142#M2809</link>
      <description>&lt;P&gt;We have confirmed the following regarding this issue and would like to inform you of the issue.&lt;/P&gt;&lt;P&gt;We suspected that the PSRAM may be affecting the circuit, so we opened JP1 in the circuit diagram uploaded yesterday and checked with the PSRAM electrically disconnected, but we were unable to write to the Flash.&lt;/P&gt;&lt;P&gt;If you have any advice, including about yesterday's post, we would appreciate it.&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;</description>
      <pubDate>Wed, 26 Mar 2025 00:16:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2068142#M2809</guid>
      <dc:creator>takagi_y</dc:creator>
      <dc:date>2025-03-26T00:16:34Z</dc:date>
    </item>
    <item>
      <title>Re: Writing QSPI Flash on MCXN947 board.</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2070746#M2822</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/247126"&gt;@takagi_y&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;"&lt;SPAN&gt;As you suggested, I replaced the Flash of FRDM-MXN947 with MX25L3233 and checked.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I was able to write when I used the same mcxn_flexspi_nor_config.c as the one I uploaded the other day and FlashConfig.h with CONFIG_OPTION0 set to 0xC0000101.&lt;/SPAN&gt;"&lt;/P&gt;
&lt;P&gt;This proves that your software configuration is fine.&lt;/P&gt;
&lt;P&gt;So I think it's still a hardware issue.&lt;/P&gt;
&lt;P&gt;Can you try connecting to Nor Flash only?&lt;/P&gt;
&lt;P&gt;Disconnect the &lt;SPAN&gt;PSRAM&amp;nbsp;&lt;/SPAN&gt;related&lt;SPAN&gt;&amp;nbsp;electrically(including DATA CLOCK CS).&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;BR&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Harry&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Mon, 31 Mar 2025 03:01:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2070746#M2822</guid>
      <dc:creator>Harry_Zhang</dc:creator>
      <dc:date>2025-03-31T03:01:38Z</dc:date>
    </item>
    <item>
      <title>Re: Writing QSPI Flash on MCXN947 board.</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2070798#M2824</link>
      <description>&lt;P&gt;Thank you for your reply.&lt;/P&gt;&lt;P&gt;Since the CEn of the PSRAM is fixed at the H level, I believe that the DATA and CLOCK of the PSRAM do not affect the QSPI Flash.&lt;/P&gt;&lt;P&gt;Are there any other possible causes?&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;</description>
      <pubDate>Mon, 31 Mar 2025 04:54:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2070798#M2824</guid>
      <dc:creator>takagi_y</dc:creator>
      <dc:date>2025-03-31T04:54:06Z</dc:date>
    </item>
    <item>
      <title>Re: Writing QSPI Flash on MCXN947 board.</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2073529#M2843</link>
      <description>&lt;P&gt;I have an additional question.&lt;/P&gt;&lt;P&gt;The PSRAM is electrically isolated, and in this state, writing can be done from the SEC tool.&lt;BR /&gt;If writing is done from the IDE in the same state, it fails.&lt;BR /&gt;If the PSRAM is affecting it, I think writing cannot be done with the SEC tool either.&lt;BR /&gt;What do you think?&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;</description>
      <pubDate>Thu, 03 Apr 2025 08:38:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2073529#M2843</guid>
      <dc:creator>takagi_y</dc:creator>
      <dc:date>2025-04-03T08:38:59Z</dc:date>
    </item>
    <item>
      <title>Re: Writing QSPI Flash on MCXN947 board.</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2075076#M2850</link>
      <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/247126"&gt;@takagi_y&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Yes, your analysis is correct.&lt;/P&gt;
&lt;P&gt;If writing can be done from the SEC tool.&lt;/P&gt;
&lt;P&gt;This proves that there is no issue with the hardware.&lt;/P&gt;
&lt;P&gt;Previously, you verified that your software had no issues with FRDM mcxn947, and now you have verified that your hardware has no issues with SEC tool,&lt;/P&gt;
&lt;P&gt;so can you work now?&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Harry&lt;/P&gt;</description>
      <pubDate>Mon, 07 Apr 2025 10:19:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2075076#M2850</guid>
      <dc:creator>Harry_Zhang</dc:creator>
      <dc:date>2025-04-07T10:19:43Z</dc:date>
    </item>
    <item>
      <title>Re: Writing QSPI Flash on MCXN947 board.</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2075539#M2851</link>
      <description>&lt;P&gt;Thank you for your reply.&lt;/P&gt;&lt;P&gt;I can write from the SEC tool, but I cannot write from MCUXpresso IDE.&lt;/P&gt;&lt;P&gt;I think there is some reason why I cannot write from MCUXpresso IDE, but I don't know what it is.&lt;BR /&gt;Could you give me some advice?&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;</description>
      <pubDate>Tue, 08 Apr 2025 00:24:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2075539#M2851</guid>
      <dc:creator>takagi_y</dc:creator>
      <dc:date>2025-04-08T00:24:58Z</dc:date>
    </item>
    <item>
      <title>Re: Writing QSPI Flash on MCXN947 board.</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2077049#M2860</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/247126"&gt;@takagi_y&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;You can&amp;nbsp;write from the SEC tool, this proves that the FCB produced by SEC is correct.&lt;/P&gt;
&lt;P&gt;So i think you can flash the correct FCB to 0x80000400.&lt;/P&gt;
&lt;P&gt;And then delete&amp;nbsp;mcxn_flexspi_nor_config.c and&amp;nbsp;mcxn_flexspi_nor_config.h in MCUXpresso.&lt;/P&gt;
&lt;P&gt;Because they generate the NEW FCB and flash in&amp;nbsp;0x80000400.&lt;/P&gt;
&lt;P&gt;And you can debug it.&lt;/P&gt;
&lt;P&gt;I tested, i generate the FCB.bin through the SEC tool. and flash it into 0x80000400.&lt;/P&gt;
&lt;P&gt;And i can debug it successfully.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Harry_Zhang_0-1744193877363.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/332272iC5E03CEE11937E36/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Harry_Zhang_0-1744193877363.png" alt="Harry_Zhang_0-1744193877363.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;To summarize, put the correct FCB into 0x80000400, and put the correct application into 0x80001000.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Harry&lt;/P&gt;</description>
      <pubDate>Wed, 09 Apr 2025 10:26:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Writing-QSPI-Flash-on-MCXN947-board/m-p/2077049#M2860</guid>
      <dc:creator>Harry_Zhang</dc:creator>
      <dc:date>2025-04-09T10:26:31Z</dc:date>
    </item>
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