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    <title>topic MCXN947 I3C IBI payload issue in MCX Microcontrollers</title>
    <link>https://community.nxp.com/t5/MCX-Microcontrollers/MCXN947-I3C-IBI-payload-issue/m-p/2056231#M2592</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I met a few issues about I3C receive IBI payload issue. Hope you can help. Appreciate.&lt;/P&gt;&lt;P&gt;When I used NXP974 as I3C master, how many payload data include MDB can we received? In my test, it seems the maximum is 8 bytes. (one MDB and seven payload data). But from the spec, it indicates that support 9 bytes include MDB. Can you help to confirm?&lt;/P&gt;&lt;P&gt;Spec :&amp;nbsp;The controller automatically stops IBI data after 9 bytes (including the mandatory data byte).&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Another issue I met is when I set the payload to 8 bytes, I do received the 8 bytes from fifo but it will enter IBI again and caused system stuck even if we didn't send new IBI from i3c target. When the payload size is less than 8 bytes, it works well.&amp;nbsp;&lt;/P&gt;&lt;P&gt;I checked the RX FIFO count from SDATACTRL, it is 8. I think it is correct. And the status of irq seems correct, it is same as normal case (0x2e00). So I guess it is correct too.&lt;/P&gt;&lt;P&gt;Then, I tried to capture the waveform by LA. I found some different between correct and incorrect case.&amp;nbsp;&lt;/P&gt;&lt;P&gt;In normal case (payload &amp;lt; 7) the whole clock period of last T-bit is low, then generate a Stop.&amp;nbsp;&lt;/P&gt;&lt;P&gt;In the wrong case, the SDA will be high in the rising edge of the T-bit clock. Then, resend clock (open-drain).&lt;/P&gt;&lt;P&gt;Do you know what happened on the NXP? Why there are different behaviors when the payload size is different?&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Wed, 05 Mar 2025 11:08:36 GMT</pubDate>
    <dc:creator>JackieZhu</dc:creator>
    <dc:date>2025-03-05T11:08:36Z</dc:date>
    <item>
      <title>MCXN947 I3C IBI payload issue</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/MCXN947-I3C-IBI-payload-issue/m-p/2056231#M2592</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I met a few issues about I3C receive IBI payload issue. Hope you can help. Appreciate.&lt;/P&gt;&lt;P&gt;When I used NXP974 as I3C master, how many payload data include MDB can we received? In my test, it seems the maximum is 8 bytes. (one MDB and seven payload data). But from the spec, it indicates that support 9 bytes include MDB. Can you help to confirm?&lt;/P&gt;&lt;P&gt;Spec :&amp;nbsp;The controller automatically stops IBI data after 9 bytes (including the mandatory data byte).&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Another issue I met is when I set the payload to 8 bytes, I do received the 8 bytes from fifo but it will enter IBI again and caused system stuck even if we didn't send new IBI from i3c target. When the payload size is less than 8 bytes, it works well.&amp;nbsp;&lt;/P&gt;&lt;P&gt;I checked the RX FIFO count from SDATACTRL, it is 8. I think it is correct. And the status of irq seems correct, it is same as normal case (0x2e00). So I guess it is correct too.&lt;/P&gt;&lt;P&gt;Then, I tried to capture the waveform by LA. I found some different between correct and incorrect case.&amp;nbsp;&lt;/P&gt;&lt;P&gt;In normal case (payload &amp;lt; 7) the whole clock period of last T-bit is low, then generate a Stop.&amp;nbsp;&lt;/P&gt;&lt;P&gt;In the wrong case, the SDA will be high in the rising edge of the T-bit clock. Then, resend clock (open-drain).&lt;/P&gt;&lt;P&gt;Do you know what happened on the NXP? Why there are different behaviors when the payload size is different?&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 05 Mar 2025 11:08:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/MCXN947-I3C-IBI-payload-issue/m-p/2056231#M2592</guid>
      <dc:creator>JackieZhu</dc:creator>
      <dc:date>2025-03-05T11:08:36Z</dc:date>
    </item>
    <item>
      <title>Re: MCXN947 I3C IBI payload issue</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/MCXN947-I3C-IBI-payload-issue/m-p/2066087#M2735</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/247624"&gt;@JackieZhu&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Yes, you are right. I3C target supports up to seven bytes of Extended IBI Data following a Mandatory Data byte.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Harry_Zhang_0-1742541579662.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/329210i055232CF13D6FFA8/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Harry_Zhang_0-1742541579662.png" alt="Harry_Zhang_0-1742541579662.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;So&amp;nbsp;&amp;nbsp;&lt;SPAN&gt;include MDB,&amp;nbsp;the maximum is 8 bytes. (one MDB and seven payload data).&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;BR&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Harry&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 21 Mar 2025 07:21:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/MCXN947-I3C-IBI-payload-issue/m-p/2066087#M2735</guid>
      <dc:creator>Harry_Zhang</dc:creator>
      <dc:date>2025-03-21T07:21:10Z</dc:date>
    </item>
    <item>
      <title>Re: MCXN947 I3C IBI payload issue</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/MCXN947-I3C-IBI-payload-issue/m-p/2269284#M4563</link>
      <description>Hi Jackie!&lt;BR /&gt;&lt;BR /&gt;We have also faced this problem in the past and reported it to NXP. We got the confirmation that this is a bug in the NXP I3C IP block. The IBI Payload Length cannot be greater than 8 bytes, and additionally, the I3C Target SHALL use the T-Bit to indicate the End Of Data (T-Bit LOW) in the last byte. The I3C IP Block, when acting as the controller, cannot emit the STOP condition if the T-Bit is HIGH.</description>
      <pubDate>Fri, 26 Dec 2025 18:49:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/MCXN947-I3C-IBI-payload-issue/m-p/2269284#M4563</guid>
      <dc:creator>martingcavallo</dc:creator>
      <dc:date>2025-12-26T18:49:30Z</dc:date>
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