<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: Enabling Data Cache in MCX Microcontrollers</title>
    <link>https://community.nxp.com/t5/MCX-Microcontrollers/Enabling-Data-Cache/m-p/2050818#M2567</link>
    <description>&lt;P&gt;Hi Harry,&amp;nbsp;&lt;BR /&gt;I was going through the reference manual and SDK drivers as you mentioned:&lt;BR /&gt;I noticed theres is&amp;nbsp;&lt;BR /&gt;* fsl_cach_lpcac.h which contains&amp;nbsp;&lt;STRONG&gt;L1CACHE_EnableCodeCache()&lt;/STRONG&gt;&lt;BR /&gt;and&lt;BR /&gt;* fsl_cache.h which contains&amp;nbsp;&lt;STRONG&gt;CACHE64_EnableCache(CACHE64_CTRL_Type *base)&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;Could&amp;nbsp;&lt;STRONG&gt;CACHE64&amp;nbsp;&lt;/STRONG&gt;be data cache and LPCAC be&amp;nbsp;&lt;STRONG&gt;Instruction cache?&lt;/STRONG&gt;&lt;/P&gt;</description>
    <pubDate>Tue, 25 Feb 2025 12:19:24 GMT</pubDate>
    <dc:creator>ge0rgeth0mas</dc:creator>
    <dc:date>2025-02-25T12:19:24Z</dc:date>
    <item>
      <title>Enabling Data Cache</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Enabling-Data-Cache/m-p/2049677#M2554</link>
      <description>&lt;P&gt;Hi,&amp;nbsp;&lt;/P&gt;&lt;P&gt;I'm testing the inference time and performance of TFLite AI Models on the NXP FRDM-MCXN947 MCUs. While I'm getting good performance using the NPU, I'm getting comparably slow inference times when not using it. I have been able to reduce inference time for other MCUs by enabling the Data Cache. I would like to know how to enable D-Cache on the NXP MCUs. Any other performance boost strategies are also welcome.&lt;/P&gt;</description>
      <pubDate>Mon, 24 Feb 2025 07:10:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Enabling-Data-Cache/m-p/2049677#M2554</guid>
      <dc:creator>ge0rgeth0mas</dc:creator>
      <dc:date>2025-02-24T07:10:12Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling Data Cache</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Enabling-Data-Cache/m-p/2050697#M2563</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/241711"&gt;@ge0rgeth0mas&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;You can refer to the&amp;nbsp;Chapter 5 in&amp;nbsp;MCX Nx4x Reference Manual.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Snipaste_2025-02-25_17-55-06.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/325515i05A75EA292912966/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Snipaste_2025-02-25_17-55-06.png" alt="Snipaste_2025-02-25_17-55-06.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;Regarding cache related APIs. &lt;/P&gt;
&lt;P&gt;You can refer to the&amp;nbsp;fsl_cache_lpcac.h in MCXN947 SDK.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Snipaste_2025-02-25_17-58-52.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/325521i2EEE5072010517D4/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Snipaste_2025-02-25_17-58-52.png" alt="Snipaste_2025-02-25_17-58-52.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Harry&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 25 Feb 2025 10:00:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Enabling-Data-Cache/m-p/2050697#M2563</guid>
      <dc:creator>Harry_Zhang</dc:creator>
      <dc:date>2025-02-25T10:00:26Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling Data Cache</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Enabling-Data-Cache/m-p/2050815#M2566</link>
      <description>&lt;P&gt;Hi Harry,&amp;nbsp;&lt;/P&gt;&lt;P&gt;Could&amp;nbsp;&lt;STRONG&gt;CACHE64&amp;nbsp;&lt;/STRONG&gt;be data cache and LPCAC be&amp;nbsp;&lt;STRONG&gt;Instruction cache?&lt;/STRONG&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 25 Feb 2025 12:16:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Enabling-Data-Cache/m-p/2050815#M2566</guid>
      <dc:creator>ge0rgeth0mas</dc:creator>
      <dc:date>2025-02-25T12:16:25Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling Data Cache</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Enabling-Data-Cache/m-p/2050818#M2567</link>
      <description>&lt;P&gt;Hi Harry,&amp;nbsp;&lt;BR /&gt;I was going through the reference manual and SDK drivers as you mentioned:&lt;BR /&gt;I noticed theres is&amp;nbsp;&lt;BR /&gt;* fsl_cach_lpcac.h which contains&amp;nbsp;&lt;STRONG&gt;L1CACHE_EnableCodeCache()&lt;/STRONG&gt;&lt;BR /&gt;and&lt;BR /&gt;* fsl_cache.h which contains&amp;nbsp;&lt;STRONG&gt;CACHE64_EnableCache(CACHE64_CTRL_Type *base)&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;Could&amp;nbsp;&lt;STRONG&gt;CACHE64&amp;nbsp;&lt;/STRONG&gt;be data cache and LPCAC be&amp;nbsp;&lt;STRONG&gt;Instruction cache?&lt;/STRONG&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 25 Feb 2025 12:19:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Enabling-Data-Cache/m-p/2050818#M2567</guid>
      <dc:creator>ge0rgeth0mas</dc:creator>
      <dc:date>2025-02-25T12:19:24Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling Data Cache</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Enabling-Data-Cache/m-p/2051468#M2568</link>
      <description>&lt;P&gt;&lt;SPAN&gt;It's great to see you exploring TFLite AI Models on the NXP FRDM-MCXN947! Enabling D-Cache can indeed enhance performance significantly. You might also look into optimizing your model size or quantizing your models for better efficiency. Speaking of performance, have you tried integrating it with gaming applications like the &lt;A href="https://snowrider3dd.github.io" target="_self"&gt;Snow Rider 3D&lt;/A&gt; game? It could be a fun way to test the capabilities of your setup!&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 26 Feb 2025 07:47:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Enabling-Data-Cache/m-p/2051468#M2568</guid>
      <dc:creator>Trappka</dc:creator>
      <dc:date>2025-02-26T07:47:21Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling Data Cache</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Enabling-Data-Cache/m-p/2052493#M2573</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/241711"&gt;@ge0rgeth0mas&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;The CACHE64 module is used to cache FlexSPI accesses.&lt;/P&gt;
&lt;P&gt;Based on&amp;nbsp; your need, you just need to enable lpcache.&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;Harry&lt;/P&gt;</description>
      <pubDate>Thu, 27 Feb 2025 03:19:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Enabling-Data-Cache/m-p/2052493#M2573</guid>
      <dc:creator>Harry_Zhang</dc:creator>
      <dc:date>2025-02-27T03:19:55Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling Data Cache</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Enabling-Data-Cache/m-p/2064417#M2714</link>
      <description>&lt;P&gt;Interesting! Have you experimented with compiler optimization flags? Often, bumping up optimization (e.g., -O3) can significantly speed up code when the NPU isn't active. Also, regarding D-Cache, check the SDK documentation for CACHE_Enable or similar functions, specifically for the MCXN947. Remember optimizing often comes down to a balancing act like in &lt;A title="Slope Game" href="https://slopegame.lol" target="_self"&gt;Slope Game&lt;/A&gt;, optimizing code versus hardware limitations for top performance. Good luck!&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 19 Mar 2025 06:55:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Enabling-Data-Cache/m-p/2064417#M2714</guid>
      <dc:creator>Slopegame</dc:creator>
      <dc:date>2025-03-19T06:55:48Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling Data Cache</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Enabling-Data-Cache/m-p/2260125#M4500</link>
      <description>&lt;P&gt;Enabling data cache can really speed up workflows and reduce repetitive processing. For those looking to plan effectively, the &lt;A href="https://persona-3reloadfusioncalculator.vercel.app/lilith-fusion-calculator" target="_self"&gt;Persona fusion strategy&lt;/A&gt; offers a clear way to anticipate outcomes and optimize results. It’s fascinating how combining the right elements can lead to unexpected efficiencies. This approach definitely makes managing complex data much more approachable.&lt;/P&gt;</description>
      <pubDate>Thu, 11 Dec 2025 11:05:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Enabling-Data-Cache/m-p/2260125#M4500</guid>
      <dc:creator>Selina_Robert</dc:creator>
      <dc:date>2025-12-11T11:05:18Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling Data Cache</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Enabling-Data-Cache/m-p/2312510#M4804</link>
      <description>&lt;P&gt;That's fascinating work! I've dabbled in similar optimization challenges before. Have you explored different quantization techniques for your TFLite models? Sometimes, even small tweaks there can make a difference when the NPU isn't engaged. Speaking of fast-paced action, it reminds me of playing &lt;STRONG&gt;&lt;A href="https://basketballstarsfree.io/" target="_self"&gt;Basketball Stars&lt;/A&gt;&lt;/STRONG&gt;! It demands quick reflexes and strategy, just like optimizing AI. You might find it a fun distraction when you need a break from the coding.&lt;/P&gt;</description>
      <pubDate>Thu, 05 Feb 2026 03:23:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Enabling-Data-Cache/m-p/2312510#M4804</guid>
      <dc:creator>RyanTyler</dc:creator>
      <dc:date>2026-02-05T03:23:06Z</dc:date>
    </item>
    <item>
      <title>Re: Enabling Data Cache</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Enabling-Data-Cache/m-p/2336411#M5053</link>
      <description>&lt;P&gt;That's interesting work on the FRDM-MCXN947! It's great you're exploring different performance optimizations. I haven't worked with that specific MCU, but data cache enabling definitely makes a difference in many cases. You might find some helpful insights from communities focused on embedded development, or perhaps even those discussing similar optimization challenges within the context of games like, ironically enough, &lt;STRONG&gt;&lt;A href="https://suikagame.lol/" target="_self"&gt;Suika Game&lt;/A&gt;&lt;/STRONG&gt;! Sometimes the approaches to efficiency in game development translate unexpectedly well. Good luck with your project!&lt;/P&gt;</description>
      <pubDate>Fri, 20 Mar 2026 08:17:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Enabling-Data-Cache/m-p/2336411#M5053</guid>
      <dc:creator>CoreyFranklin</dc:creator>
      <dc:date>2026-03-20T08:17:04Z</dc:date>
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  </channel>
</rss>

