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    <title>topic Re: Drive Strength Enable DSE vs DSE1 in MCX A in MCX Microcontrollers</title>
    <link>https://community.nxp.com/t5/MCX-Microcontrollers/Drive-Strength-Enable-DSE-vs-DSE1-in-MCX-A/m-p/1976728#M1794</link>
    <description>&lt;P&gt;Hello&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/242119"&gt;@JosG&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;Thanks for contacting NXP Tech Support.&lt;/P&gt;
&lt;P&gt;For more information about DSE, you can find it in the Data Sheet. It is mentioned that "PE, PS, SRE, ODE and DSE are supported in the Pin Control register of all types of IO. &lt;STRONG&gt;5VTol and HD pads support two DSE bits in the Pin Control register of the pin.&lt;/STRONG&gt;" In the PCRn register, DSE and DSE1 are the names of these two bits. Not all PCRn registers have two DSE bits; some only have one. The details can be found in the Reference Manual. Based on this, the I/O pin diagram structure is easy to understand. The DSE indicated on it includes both DSE and DSE1.&lt;/P&gt;
&lt;P&gt;You can also find some useful information in the Data Sheet. For example, as mentioned on page 23, as shown in the following figure:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Celeste_Liu_0-1729233125335.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/305425iC061C8E05578E419/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Celeste_Liu_0-1729233125335.png" alt="Celeste_Liu_0-1729233125335.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;For a detailed introduction to PCRn[DSE], you can refer to the figure below.&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Celeste_Liu_1-1729233170952.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/305426i6A41D513A4348E01/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Celeste_Liu_1-1729233170952.png" alt="Celeste_Liu_1-1729233170952.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I hope the above information is useful to you.&lt;/P&gt;
&lt;P&gt;Best Regards,&lt;/P&gt;
&lt;P&gt;Celeste&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Fri, 18 Oct 2024 06:34:08 GMT</pubDate>
    <dc:creator>Celeste_Liu</dc:creator>
    <dc:date>2024-10-18T06:34:08Z</dc:date>
    <item>
      <title>Drive Strength Enable DSE vs DSE1 in MCX A</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Drive-Strength-Enable-DSE-vs-DSE1-in-MCX-A/m-p/1975898#M1787</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;I have some doubts about drive strength configuration in MCX A micros:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="JosG_0-1729155120604.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/305214i350188C6B9DF518F/image-size/medium?v=v2&amp;amp;px=400" role="button" title="JosG_0-1729155120604.png" alt="JosG_0-1729155120604.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;What is the difference between DSE and DSE1 in PCRn register? Where is it DSE1 integrated in the I/O pin diagram structure drawing? I’m not able to clearly understand the difference…&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="JosG_1-1729155120630.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/305215iF3E160A62265B934/image-size/medium?v=v2&amp;amp;px=400" role="button" title="JosG_1-1729155120630.png" alt="JosG_1-1729155120630.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;Thanks!&lt;/P&gt;</description>
      <pubDate>Thu, 17 Oct 2024 08:54:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Drive-Strength-Enable-DSE-vs-DSE1-in-MCX-A/m-p/1975898#M1787</guid>
      <dc:creator>JosG</dc:creator>
      <dc:date>2024-10-17T08:54:03Z</dc:date>
    </item>
    <item>
      <title>Re: Drive Strength Enable DSE vs DSE1 in MCX A</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Drive-Strength-Enable-DSE-vs-DSE1-in-MCX-A/m-p/1976728#M1794</link>
      <description>&lt;P&gt;Hello&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/242119"&gt;@JosG&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;Thanks for contacting NXP Tech Support.&lt;/P&gt;
&lt;P&gt;For more information about DSE, you can find it in the Data Sheet. It is mentioned that "PE, PS, SRE, ODE and DSE are supported in the Pin Control register of all types of IO. &lt;STRONG&gt;5VTol and HD pads support two DSE bits in the Pin Control register of the pin.&lt;/STRONG&gt;" In the PCRn register, DSE and DSE1 are the names of these two bits. Not all PCRn registers have two DSE bits; some only have one. The details can be found in the Reference Manual. Based on this, the I/O pin diagram structure is easy to understand. The DSE indicated on it includes both DSE and DSE1.&lt;/P&gt;
&lt;P&gt;You can also find some useful information in the Data Sheet. For example, as mentioned on page 23, as shown in the following figure:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Celeste_Liu_0-1729233125335.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/305425iC061C8E05578E419/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Celeste_Liu_0-1729233125335.png" alt="Celeste_Liu_0-1729233125335.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;For a detailed introduction to PCRn[DSE], you can refer to the figure below.&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Celeste_Liu_1-1729233170952.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/305426i6A41D513A4348E01/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Celeste_Liu_1-1729233170952.png" alt="Celeste_Liu_1-1729233170952.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I hope the above information is useful to you.&lt;/P&gt;
&lt;P&gt;Best Regards,&lt;/P&gt;
&lt;P&gt;Celeste&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 18 Oct 2024 06:34:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Drive-Strength-Enable-DSE-vs-DSE1-in-MCX-A/m-p/1976728#M1794</guid>
      <dc:creator>Celeste_Liu</dc:creator>
      <dc:date>2024-10-18T06:34:08Z</dc:date>
    </item>
    <item>
      <title>Re: Drive Strength Enable DSE vs DSE1 in MCX A</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Drive-Strength-Enable-DSE-vs-DSE1-in-MCX-A/m-p/1976850#M1797</link>
      <description>Thanks Celeste!</description>
      <pubDate>Fri, 18 Oct 2024 08:19:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Drive-Strength-Enable-DSE-vs-DSE1-in-MCX-A/m-p/1976850#M1797</guid>
      <dc:creator>JosG</dc:creator>
      <dc:date>2024-10-18T08:19:08Z</dc:date>
    </item>
    <item>
      <title>Re: Drive Strength Enable DSE vs DSE1 in MCX A</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/Drive-Strength-Enable-DSE-vs-DSE1-in-MCX-A/m-p/1977485#M1801</link>
      <description>&lt;P&gt;I'm glad I could help you. Any new issues, welcome to create the new thread.&lt;/P&gt;</description>
      <pubDate>Sat, 19 Oct 2024 05:11:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/Drive-Strength-Enable-DSE-vs-DSE1-in-MCX-A/m-p/1977485#M1801</guid>
      <dc:creator>Celeste_Liu</dc:creator>
      <dc:date>2024-10-19T05:11:01Z</dc:date>
    </item>
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