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    <title>topic Re: One MCLK for two SAI-Interfaces in MCX Microcontrollers</title>
    <link>https://community.nxp.com/t5/MCX-Microcontrollers/One-MCLK-for-two-SAI-Interfaces/m-p/1957962#M1664</link>
    <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;The transmitter and receiver can independently select between the bus clock and up to three audio master clocks to generate the bit clock. The \consideration is if you use a shared MCLK signal for your SAI ports, SAI5 or SAI6 should be configured in Synchronous mode between ports.&lt;/P&gt;
&lt;P&gt;Best regards.&lt;/P&gt;</description>
    <pubDate>Thu, 19 Sep 2024 19:15:35 GMT</pubDate>
    <dc:creator>JorgeCas</dc:creator>
    <dc:date>2024-09-19T19:15:35Z</dc:date>
    <item>
      <title>One MCLK for two SAI-Interfaces</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/One-MCLK-for-two-SAI-Interfaces/m-p/1957512#M1662</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I use i.MX8m mini and, and I want&amp;nbsp;to operate two SAI-Interfaces at the same time.&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;It is possible to use a single MCLK for two SAI-interfaces (e.g. SAI5 and SAI6)????&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;If yes, are there any&amp;nbsp;Disadvantages ??&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 19 Sep 2024 09:09:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/One-MCLK-for-two-SAI-Interfaces/m-p/1957512#M1662</guid>
      <dc:creator>HelloWorld121</dc:creator>
      <dc:date>2024-09-19T09:09:23Z</dc:date>
    </item>
    <item>
      <title>Re: One MCLK for two SAI-Interfaces</title>
      <link>https://community.nxp.com/t5/MCX-Microcontrollers/One-MCLK-for-two-SAI-Interfaces/m-p/1957962#M1664</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;The transmitter and receiver can independently select between the bus clock and up to three audio master clocks to generate the bit clock. The \consideration is if you use a shared MCLK signal for your SAI ports, SAI5 or SAI6 should be configured in Synchronous mode between ports.&lt;/P&gt;
&lt;P&gt;Best regards.&lt;/P&gt;</description>
      <pubDate>Thu, 19 Sep 2024 19:15:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCX-Microcontrollers/One-MCLK-for-two-SAI-Interfaces/m-p/1957962#M1664</guid>
      <dc:creator>JorgeCas</dc:creator>
      <dc:date>2024-09-19T19:15:35Z</dc:date>
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