topic Re: MCXN ENET RMII Clock in MCX Microcontrollers

MCXN ENET RMII Clock

Vagni — Mon, 29 Jul 2024 10:22:35 GMT

I started evaluating MCXN547 ENET peripheral functionalities on MCX-N5XX-EVK board.

On that board the Ethernet PHY clock input can be either of the following:

OSC_50M clock from an external 50 MHz crystal oscillator (Y7) enabled by JP50 jumper open.
ENET0_TXCLK clock received through the MCU P1_4 port

I checked the mcxn5xxevk_lwip_dhcp_bm SDK 2.16 example with JP50 open and the EVK board properly receives a IPv4 configuration from my network DHCP.

Then I replaced in the lwip_dhcp_bm.c source file the PHY input clock assertion:

CLOCK_AttachClk(MUX_A(CM_ENETRMIICLKSEL, 0));

with my new assertion:

/* Use internal reference clock. */ /* attach PLL0_CLK_clock to ENETRMII */ CLOCK_AttachClk(kPLL0_to_ENETRMII); /*!< Set up ENETRMIICLKDIV divider */ CLOCK_SetClkDiv(kCLOCK_DivEnetrmiiClk, 3U);

and I build and check the same mcxn5xxevk_lwip_dhcp_bm demo application with JP50 closed (using ENET0_TXCLK clock).

But now the PHY state is "down" and Auto-negotiation fails till finally PHY state becomes "up", but then returns again "down" and DHCP configuration is never received.

PLL0_CLK should be set to 150MHz by BOARD_InitBootClocks() function, right?.

How to properly drive the Ethernet PHY with the ENET0_TXCLK clock from MCU ?

Re: MCXN ENET RMII Clock

Joey_z — Tue, 30 Jul 2024 10:38:57 GMT

hi，Vagni

Thank you for your interest in NXP Semiconductor products and the opportunity to serve you, I will gladly help you with this.

View schematic SCH-55277.pdf as shown below. If you want to use ENET0_TXCLK, try Connect JP13 2-3 pin. Populate R274 to sync reference clock, close JP50.

Wish it helps you.

If you still have question about it,please kindly let me know.

Xu Zhang

Re: MCXN ENET RMII Clock

Vagni — Tue, 30 Jul 2024 12:45:45 GMT

Thank you Xu Zhang,

Yes, I have JP13 closed on 2-3 pin, R274 populated and JP50 closed.

Are my above assertions (ENETRMIICLKSEL = 1, PLL0 clock 150MHz ; ENETRMIICLKDIV = 2, divide by 3) right to output the 50MHz clock from ENET0_TXCLK? I miss something else?

With the original assertion (ENETRMIICLKSEL = 0, no clock) and JP50 open it works properly.

Re: MCXN ENET RMII Clock

Vagni — Thu, 01 Aug 2024 12:31:18 GMT

I see ENET RMII Clock Divider register ENETRMIICLKDIV has the UNSTAB status flag, the RESET flag and the HALT run/stop flag. So I tried the following new code to enable the ENET0_TXCLK clock output:

/* attach PLL0_CLK_clock 150MHz to ENETRMII */ CLOCK_AttachClk(kPLL0_to_ENETRMII); /*!< Set up ENETRMIICLKDIV divider to 3 (50MHz) */ CLOCK_SetClkDiv(kCLOCK_DivEnetrmiiClk, 3U); SYSCON->ENETRMIICLKDIV &= (uint32_t) ~(SYSCON_ENETRMIICLKDIV_HALT_MASK | SYSCON_ENETRMIICLKDIV_RESET_MASK); /* Wait until clock change completes */ while ((SYSCON->ENETRMIICLKDIV & SYSCON_ENETRMIICLKDIV_UNSTAB_MASK) != 0U) { }

But the issue is still present: the Ethernet PHY is quite always down.

Actually, with my scope I see a very unstable 50MHz clock output from the MCU in this condition. With the external oscillator enabled the 50MHz clock signal is good.

How to properly set ENETRMIICLKDIV to have 50MHz output from PLL0 150MHz input through the Ethernet RMII Clock Selection MUX ?

Re: MCXN ENET RMII Clock

Joey_z — Sun, 17 Nov 2024 03:23:04 GMT

hi,Vagni

Our default configuration is using FIRC48M for the clock source of the PLL0, which is derived from FRO144M and has the maximum error of 3% across the device's full temperature range, along with 200ps jitter RMS which exceeds the clock specification required for RMII operation (see attached images).

Please check the attached project which uses on-board 24MHz crystal oscillator to provide low jitter and accurate clock source to PLL0 module, and uses PLL0 as RMII clock source.

Since RMII clock frequency is relatively high (50MHz), so the oscilloscope and the measurement set-up (i.e. ground-loop) needs to be carefully adjusted to avoid signal integrity (SI) issues introduced by the improper measurement system. Please check the attached scope image for the 50MHz output from P1_4.

I put the modified program in the attachment, please close JP50 and try again.

Xu Zhang

Re: MCXN ENET RMII Clock

Vagni — Tue, 06 Aug 2024 10:21:53 GMT

Thank you Xu Zhang,

Now it works with PLL0 sourced by the on-board 24MHz crystal oscillator.