topic SDK_2_16_000_FRDM-MCXA153 API(CLOCK_FROHFTrimConfig()) Bug in MCX Microcontrollers

SDK_2_16_000_FRDM-MCXA153 API(CLOCK_FROHFTrimConfig()) Bug

lmst-mcu — Sat, 20 Jul 2024 15:40:51 GMT

0 is not written in FIRCCSR.LK, so the remaining bits cannot be modified.

Re: SDK_2_16_000_FRDM-MCXA153 API(CLOCK_FROHFTrimConfig()) Bug

Alphabert_Liu — Wed, 24 Jul 2024 10:40:20 GMT

From the MCX A153 Reference Manual 22.6.3.1, we can find that FIRC normal configuration write 0 to FIRCCSR[LK] to unlock FIRCCSR.

And I find that in my MCXA153 SDK 2.16 configuration, the register in fsl_clock.c has been successfully unlocked.

Could you please tell me where the problem lies in your case?

Best Regard

Liu

Re: SDK_2_16_000_FRDM-MCXA153 API(CLOCK_FROHFTrimConfig()) Bug

lmst-mcu — Wed, 24 Jul 2024 16:09:16 GMT

Hi. @Alphabert_Liu

Thank you for the response.

Here is a screenshot of my file contents (full file attached), it seems that the LK bit is not cleared in this function.

Re: SDK_2_16_000_FRDM-MCXA153 API(CLOCK_FROHFTrimConfig()) Bug

Alphabert_Liu — Thu, 25 Jul 2024 03:40:47 GMT

Hello @lmst-mcu ,

In my understanding, the default value of the LK bit is 0, and in the following code, the LK bit of this register is also set to 0.

/* Set trim mode. */ SCG0->FIRCCSR = (uint32_t)config.trimMode;

You can connect your development board and debug the demo from the SDK you are using. In the debug process, navigate to the FIRCCSR register located within SCG0 in the "Perapherals+" column value of the bit you are interested in.

Best Regard

Liu